User's Manual

Model 1150A DVOR
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
6-13
f. M
easure the voltage at 1A3A1TP2, carrier phase loop control voltage. This voltage must be between 2
volts and 8 volts.
g. Adjustment of the Transmitters>> Configuration >>Carrier PLL control can result in two different settings
that result in 0.0 +/- 0.05 volts on TP1. If TP2 is below 2 volts, or above 8 volts repeat steps e and f until
the result 0.0 +/- 0.05 volts on TP1 with TP2 between 2 and 8 volts is achieved.
h. Connect a frequency counter to 1A3A11J2, the SMA connector on the front panel of the Tx 2 Synthesizer
Assembly.
i. Measure the output frequency of the 1A3A11J2 Frequency Synthesizer Assembly. If the measured
frequency is outside the Operational Tolerance of Table 4-1(c) then perform the following steps:
j.
i. Remove power from the DVOR.
ii. Remove the Frequency Synthesizer 1A3A11 from the VOR cabinet.
iii. Connect the 1A3A11 Frequency Synthesizer Assembly to the DVOR with extender board.
iv. Apply power to the DVOR. Turn on Tx 2. Place the Monitor in Bypass.
v. The 10.000 MHz TCXO (Y1) in the Frequency Synthesizer Assembly may be adjusted to correct
the operating frequency. Small adjustments can be made to Y1 with the R27 potentiometer to
achieve this. Once the TCXO is set the station frequency should be within the Initial Tolerance of
Table 4-1(c).
vi. Replace the Frequency Synthesizer Assembly in the system cabinet.
vii. Apply power to the DVOR.
k. Connect a DMM to the carrier phase loop error voltage at TP1 on the 1A3A11 Frequency Synthesizer
Assembly front panel.
l. Log in to the PMDT and select Transmitters>> Configuration. Adjust Tx 2 Carrier PLL control from 0 to
100% to achieve 0.0 +/- 0.05 volts on TP1.
m. Measure the voltage at 1A3A11 TP2, carrier phase loop control voltage. This voltage must be between 2
volts and 8 volts.
n. Adjustment of the Transmitters>> Configuration.>> Carrier PLL control can result in two different settings
that result in 0.0 +/- 0.05 volts on TP1. If TP2 is below 2 volts, or above 8 volts repeat steps e and f until
the result 0.0 +/- 0.05 volts on TP1 with TP2 between 2 and 8 volts is achieved.
6.4.15
DVOR Sideband Amplifier Alignment
The following procedure is to be used to optimize the sideband generator amplifiers for operation. Instructions are
provided using the 1A4A1 lower Sideband Generator Assembly; substitute 1A4A2 when performing the procedures
on Tx 1 upper Sideband Generator Assembly. Substitute 1A4A5 when performing the procedures on Tx 2 lower
Sideband Generator Assembly or substitute 1A4A6 when performing the procedures on transmitter Tx 2 upper
Sideband Generator Assembly.
a. Turn the DVOR power off.
b. Pull 1A4A1 forward and move the jumper at J11 to the position shown in Table 6-2 below.
c. Place the 1A4A1 back into the rack.
d. Turn the DVOR power on. Turn on the Transmitter and place in bypass.
e. Refer to Figure 3-66. Connect a DVM to 1A4A1 TP4. Adjust 1A4A1R1 for DVM voltage per Table 6-2
for the frequency of operation as a starting point. The actual value may change due to component tolerance.
f. Connect a DVM to 1A4A1 TP10. Adjust 1A4A1R4 for DVM voltage per Table 6-2 for the frequency of
operation.
g. Connect a DVM to 1A4A1 TP1. Adjust 1A4A1R1 for 0.90 to .95 Vdc.
h. Connect a DVM to 1A4A1 TP5. Adjust 1A4A1R1 for 0.89 to .91 Vdc.
i. Connect DVM to 1A4A1TP4. Verify that the voltage is between 2 and 9 Vdc.
j. If the voltage is within this range then move to step n below. If not within this range then perform steps j
through m below.
k. Turn off power.
l. Pull 1A4A1 forward and move the jumper at J11 from the present position (connected from 1 to 2 or
connected from 3 to 4) to the opposite position.
m. Place the 1A4A1 back into the rack.