User's Manual

Model 1150A DVOR
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
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The antenna switch signals are applied to PLD U4. PLD U4 is programmed to perform all decoding and distribution
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f the antenna and transfer signals. The clock signal provides a synchronous timing signal for all switching
activities.
The ground check switch control lines are translated to TTL levels by differential line receiver U3.
If the automatic ground check feature is enabled at J5, the ground check control lines are added as an offset inside
PLD U4. Each increment of the ground check control is added as an offset of 3 to the antenna selected by the
DVOR switch control lines.
U4 drives quad converter U7. U7 translates the antenna select data, which is referenced to TTL levels, into CMOS
levels (+5V and -10V). The data from U7 is next applied to 4-to-16 line decoder U12.
U4 uses the LOW to HIGH transition of the 720 Hz clock signal to control the timing of the odd antenna switching
signals. U4 uses the HIGH to LOW transition of the clock signal to control even antenna switching signals. The
time difference is 1/1440th of a second which is the timing difference between a sine and cosine radiated sideband
signal.
U12 decodes the antenna select 4-bit data code to select one of the twelve active outputs used in the 48 antenna
system. Outputs 13, 14, 15, and 16 are not used. The twelve lines are normally HIGH (+5 volts). When an output
line is selected, it is pulled LOW (-10 volts). Each output line feeds the A input of a decoder driver circuit (U6
through U11, U13 through U16 and U18 through U21). The B and C inputs are tied to +5 volts while the D input is
tied to -10 volts. The segment driver outputs of each display driver are uniquely paralleled to provide the necessary
drive current to operate the RF signal switching pin diodes. Effectively, there are two outputs from each display
driver: one is designated the “ON” line, and the other is the “OFF” line. U12 decoder output SNOT controls
display driver U8 which changes the ON and OFF control signals on Commutator antenna control lines OFF 1 and
25, and ON 1 and 25. U12 decoder output S1NOT controls U13 which controls lines OFF 3 and 27, and ON 3 and
27.
OFF 1 and 25 is labeled 1A and ON1 & 25 is labeled 14B on the 012104-0001 Commutator CCA. Also OFF 3 and
27 and ON 3 and 27 are labeled 2A and 15B on the Commutator CCA.
To simplify the discussion of the operation of the decoder driver signals, only the action of U8 will be examined.
U8 controls the 1A and 14B ON and OFF lines. If U8 is not selected by U12, then the ON line will have a potential
of -10 Vdc and the OFF line will have a potential of +5 Vdc. When U12 selects U8, the ON line switches to +5 Vdc
and the OFF line switches to -10 Vdc. This condition exists for the entire time that the selected antenna will radiate,
which is 1/720 of a second.
U4 also outputs signals used to generate an ODD_XFR and an ODD XFR NOT signal. PLD U4 outputs a signal to
the inverting input of voltage comparator U17A. The non-inverting input of U17A is referenced at approximately
1.5 volts by a voltage divider network which consists of resistors R14 and R15. When U4 outputs a logic LOW, it is
inverted by U17A to a HIGH which turns off Q2. When Q2 turns off, Q1 is turned on by self- biasing resistor RN6
section 3-14. With Q1 on, a potential of approximately -10 Vdc is applied to the ODD XFR line to the Commutator
CCA.
The LOW output from U4 is also applied to the non-inverting input of U17B. U17B has a +1.5 Vdc bias applied to
its inverting input by R14 and R15. The LOW in makes U17B output a LOW which turns on transistor Q4. The
emitter of Q4 is tied to VCC. With Q4 turned on, a positive voltage is applied to the base of Q3 and the anode of
CR30. The positive bias on the base of Q3 keeps Q3 turned off. However, CR30 becomes forward biased and a
positive potential of approximately +5 Vdc is applied to the ODD XFR NOT line to the Commutator.
When the output of U4 changes to a HIGH, Q2 and CR29 in the ODD XFR section are biased on and Q3 in the
ODD XFR NOT section is biased. This changes the polarity of the signals on the ODD XFR and ODD XFR NOT
lines. The ODD XFR and ODD XFR NOT changes state every 1/60th of a second.