User's Manual

Model 1150A DVOR
ii Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
TABLE OF CONTENTS (cont.)
Paragraph
# Description Page #
2.2 OPERATING PRINCIPLES.................................................................................................................2-1
2.2.1 DVOR Antenna Principles....................................................................................................................2-3
2.3 DVOR TRANSMITTER THEORY OF OPERATION........................................................................2-3
2.3.1 Simplified System Block Diagram........................................................................................................2-3
2.3.1.1 Electronics Cabinet (Unit 1)..................................................................................................................2-6
2.3.2 System Block Diagram Theory.............................................................................................................2-6
2.3.2.1 Frequency Synthesizer (1A3A1, 1A3A11)...........................................................................................2-7
2.3.2.1.1 Frequency Synthesizer Block Diagram Theory ....................................................................................2-7
2.3.2.1.2 Frequency Synthesizer (1A3A1, 1A3A11) Detailed Circuit Theory ....................................................2-9
2.3.2.1.2.1 Frequency Reference Circuitry .............................................................................................................2-9
2.3.2.1.2.2 Carrier PLL Synthesizer Circuitry ......................................................................................................2-10
2.3.2.1.2.3 Carrier Phase Control Loop ................................................................................................................2-12
2.3.2.1.2.4 Sideband RF Generation Loops ..........................................................................................................2-14
2.3.2.2 Audio Generator CCA (1A7, 1A23) Theory.......................................................................................2-15
2.3.2.2.1 Audio Generator CCA Block Diagram Theory...................................................................................2-15
2.3.2.3 Audio Generator CCA Detailed Circuit Theory..................................................................................2-17
2.3.2.4 CSB Power Amplifier Assembly (1A5A3, 1A5A4) ...........................................................................2-19
2.3.2.4.1 CSB Power Amplifier Assembly Block Diagram Theory ..................................................................2-19
2.3.2.4.2 Power Amplifier Assembly Detailed Circuit Theory..........................................................................2-20
2.3.2.5 Bi-Directional Coupler (1DC1)...........................................................................................................2-22
2.3.2.6 Sideband Generator Assembly (1A4A1, 1A4A2, 1A4A6, 1A5A7)....................................................2-22
2.3.2.6.1 Sideband Generator Assembly Block Diagram Theory......................................................................2-22
2.3.2.6.2 Sideband Generator CCA Detailed Circuit Theory.............................................................................2-24
2.3.2.7 RF Monitor Assembly (1A4A4) Theory.............................................................................................2-27
2.3.2.8 RF Monitor Assembly Block Diagram Theory...................................................................................2-27
2.3.2.8.1 RF Monitor Assembly (1A2) Detailed Circuit Theory .......................................................................2-28
2.3.2.9 RMS Processor Block Diagram Theory..............................................................................................2-30
2.3.2.9.1 RMS CCA Detailed Theory................................................................................................................2-32
2.3.2.10 Facilities CCA Theory ........................................................................................................................2-34
2.3.2.10.1 Facilities CCA Detailed Theory..........................................................................................................2-36
2.3.2.11 Interface CCA Theory.........................................................................................................................2-38
2.3.2.12 Interface CCA Block Diagram Theory ...............................................................................................2-38
2.3.2.12.1 Interface CCA Detailed Theory ..........................................................................................................2-39
2.3.2.13 AC Power Monitor CCA Theory........................................................................................................2-40
2.3.2.13.1 AC Power Monitor CCA Block Diagram Theory...............................................................................2-41
2.3.2.13.2 AC Power Monitor CCA Detailed Theory..........................................................................................2-41
2.3.2.14 Local Control Unit Theory..................................................................................................................2-42
2.3.2.14.1 Local Control Unit Block Diagram Theory ........................................................................................2-43
2.3.2.14.1.1 DC to DC Converter ...........................................................................................................................2-43
2.3.2.14.1.2 Power Fail Detectors...........................................................................................................................2-43
2.3.2.14.1.3 Key Switch Registers..........................................................................................................................2-43
2.3.2.14.1.4 Parallel Interface.................................................................................................................................2-43
2.3.2.14.1.5 1.8432MHz Oscillator/Divider Chains ...............................................................................................2-44
2.3.2.14.1.6 Positive Alarm Register ......................................................................................................................2-44
2.3.2.14.1.7 Negative Alarm Register.....................................................................................................................2-44
2.3.2.14.1.8 20 Second Delay Counter ...................................................................................................................2-44
2.3.2.14.1.9 LCU Transfer Control State Machine #1 and #2 and Discrete Controls.............................................2-45
2.3.2.14.1.10 LED Control........................................................................................................................................2-45
2.3.2.14.1.11 Audible Alarm ....................................................................................................................................2-45
2.3.2.14.1.12 Monitor Alarm Interface.....................................................................................................................2-45
2.3.2.14.1.13 Station Control Logic..........................................................................................................................2-45