User's Manual

MODEL 2130 MARKER BEACON
2-14 Rev. A April, 2005
This document contains proprietary information and such information may not be disclosed to others for any
purposes without written permission from SELEX Sistemi Integrati Inc.
Each of the two +12 VDC sources used to power the board are monitored by comparator U10. The two comparator
circuits are identical, so the following discussion will explain the monitoring of the 1_+12 VDC supply. The +12 VDC
supply voltage is reduced to approximately +2.7 VDC by a voltage divider network consisting of R33 and R37. This
voltage is connected to the positive input of comparator U10A. The +3.3 VDC VCC supply is reduced to 2.18 VDC by
another voltage divider network, R30 and R31. This voltage is connected to the negative input of U10A. When the +12
VDC supply is at a normal voltage, the positive input to U10A is higher than the negative input so the output of the
comparator will be at a high logic level. Since the output of the comparator is an open collector, R32 is necessary to pull it
high. When the voltage of the +12 VDC supply falls below approximately +9.60 VDC, the voltage at the positive input of
U10A will fall below +2.18V and cause the output of U12A to go to a low logic level.
2.3.3.2.2 Pushbutton Switches and LED Display
The LCU accepts control input from the operator through momentary contact pushbutton switches and presents status
information for the Marker Beacon station through a series of light emitting diodes (LEDs). The pushbutton switch
circuitry is implemented by using a pull up resistor to +3.3V to produce a high logic level and using a pushbutton switch
to momentarily ground it to produce a low logic level. Switches that provide a toggling or sequencing function (where a
multiple push would give a different result from a single push) are de-bounced by logic within the EPLDs (U1 and U3).
For other switches, a repetitive contact or bounce will not have a noticeable affect.
The board uses three different colors of LEDs: red, yellow, and green. Each of the three colors has a slightly different
forward bias voltage and efficiency. Because of this, two different values of series resistor are used in order to create the
same degree of perceived brightness. A lamp test pushbutton is implemented in the LCU in order to turn on all the LEDs
to confirm their functionality. When the lamp test switch, S3, is pushed, logic within U1 and U3 causes all outputs to
LEDs to be driven low, lighting the LEDs.
2.3.3.2.3 Parallel Interface
The RMS communicates with the LCU and the Cabinet Interface Unit (CI) through an eight bit parallel bus interface. In
order to keep the design of the peripheral (LCU or CI) simple, the RMS controls all the communication on the interface.
The RMS reads and writes to the peripheral circuitry with no handshaking. The interface consists of an eight bit bi-
directional address/data bus, an address strobe, a write strobe, and a read enable. In order to achieve sufficient noise
immunity, the address strobe and the data write strobe are driven differentially through an RS-422 interface IC, U4. The
remainder of the interface is driven to 3.3V CMOS logic levels.
The parallel interface uses the following signals:
Address/Data Bus The eight bit bi-directional address/data buss with multiplexed address.
Address Strobe A differentially driven pulse from the RMS to latch address information
into the peripheral.
Data Write Strobe A differentially driven pulse from the RMS to write data to the peripheral.
Data Read Enable A pulse from the RMS to enable data from the peripheral to be placed on
the data bus.
The RMS has the ability to read the status and control the operation of the Marker Beacon station through a parallel
interface. Data transfer is accomplished by first placing an address on the bus and cycling the address strobe (asserting
and then de-asserting the address strobe signal). The LCU latches and decodes the address within the EPLD's U1 and
U3. For a read operation, the read enable is then asserted which tells the LCU circuitry to place the appropriate data on
the data bus. For a write operation, the RMS places data on the data bus, then cycles the Data Write Strobe (asserting
and de-asserting the write strobe signal.) The address decoding circuitry within the EPLD's decodes eight addresses,
starting at (hexadecimal) 80. To buffer the EPLD's, a bus transceiver U21 is used on the data bus to provide CMOS logic
thresholds to/from the parallel interface.