User's Manual

MODEL 2130 MARKER BEACON
2-12 Rev. A April, 2005
This document contains proprietary information and such information may not be disclosed to others for any
purposes without written permission from SELEX Sistemi Integrati Inc.
2.3.3.1.3 Key Switch Registers
Front panel switches are de-bounced and held in the Key Switch Registers pending processing by the LCU transfer state
machines. Commands received from the RMS via the parallel interface also control the contents of the Key Switch
Registers. The registers will hold the last command received until the LCU transfer state machine processes the
command.
2.3.3.1.4 Parallel Interface
The interface to the RMS is via a parallel data bus consisting of eight (8) data bits, an Address Command line, a Write
Command line, and a Read Command line. The sequence to access internal registers within the LCU consist of the
address being placed on the data bus followed by the strobing of the Address Command line to latch the address into the
internal address register. This is followed by the Read Command line driven true to facilitate a read from the latched
address. For a write command, the address is followed by the data to be written to the LCU followed by strobing the
Write Command line.
Alarm Configuration, Bypass Commands, Key Commands, and basic LCU configuration are some of the bits controlled by
the RMS via the parallel interface. State machine Status, Power-fail Status, System Configuration bits (SCON), and
Local/Remote status are some of the status bits that are readable by the RMS via the parallel interface.
2.3.3.1.5 1.8432MHz Oscillator/Divider Chains
Refer to Figure 2-4. The LCU employs a 1.8432MHz crystal oscillator to produce all frequencies required by the design.
The frequency is divided by 512 to produce 3600Hz used to produce the audible alarm tone and the Transmit On clocks
driven back to the monitors. The signal is further divided by 8 to produce 450Hz used as the system clock within the
design. This signal is divided by 45 to produce 10Hz used in the 20 second delay counter and the Key De-bounce
circuits.
Figure 2-4 1.8432 MHz Oscillator/Divider Chains