User's Manual

MODEL 2130 MARKER BEACON
2-8 Rev. A April, 2005
This document contains proprietary information and such information may not be disclosed to others for any
purposes without written permission from SELEX Sistemi Integrati Inc.
All address and data lines are buffered through drivers U57, U58, U59, U60, and U61 before connecting to any memory-
mapped device except those to the U4 SDRAM, which are directly connected to U8. The drivers reduce the address and
data line capacitance seen by the U8 microcontroller so that the U4 SDRAM may operate at very high speeds.
The CR5 STATUS light emitting diode (LED) provides visual indication of proper operation of the U8 microcontroller and
that RADIO_V+ power is present.
Three grounds are utilized on the RMS CCA. Earth (EGND) ground is the drain path for all transient voltage suppression
(TVS) devices. The E1 lug and several mounting holes provide the route for EGND to leave the board. EGND is
referenced to digital ground (DGND) through inductor L2. DGND is the common point for all high-speed, high current
signals and is referenced to analog ground (AGND) through resistor R35. AGND is the quiet common point for signals
that must be measured accurately or maintain stable levels.
The U15 real-time clock (RTC) keeps time, day, week, and year information and is clocked by oscillator U9. Both U15 and
U9 are battery-backed by battery B1. Battery B1 can be disconnected at header JP3, usually only done for storage or
shipment of the RMS CCA or replacement of B1. The U15 RTC communicates serially to the U8 microcontroller at U15-6
and U15-5.
The U8 microcontroller and U1/U2 flash ROMs can be programmed and debugged in the factory using the J8 emulator
and J9 SPI Boot headers.
The DB37 J1 BCPS connector’s primary function is routing analog signals between the BCPS and
RMS/MKR1/MKR2/LCU CCAs. The Marker1 J3 and Marker2 J4 connectors are both DB25 types while the J2 LCU is a 60
pin shrouded header.
Input buffer U45 is used to read the states of REMOTE/*LOCAL (J2-19), BATT1_FAULT (J1-37), BATT2_FAULT (J1-
36), ON_BATT1 (J1-35), ON_BATT2 (J1-34), and *TEST (J2-44); all of which are pulled up by resistor network RN9.
*TEST when low will cause the lighting of all LEDs on the LCU and BCPS CCAs but does not affect the RMS, FFMX, or
Marker BeaconX LEDs.
Input buffer U44 is used to read the states of SPARE_DIN1 (TB2-2), SPARE_DIN2 (TB2-3), SPARE_DIN3 (TB2-4),
SPARE_DIN4 (TB2-5), DED/*RADIO, DIALUP/*EXT, SMOKE_DETECTOR (TB1-10), and INTRUSION_SENSOR (TB1-
11); all of which are pulled up by resistor network RN8 and resistors R106 and R107. DED/*RADIO and DIALUP/*EXT
are strapped at header JP1 to determine tip/ring versus RS232 modem operation.
Latches U38 and U32, input buffer U42, and RS422 driver U34 comprise the bidirectional parallel port interface PPI
between the RMS and the LCU CCAs. Data transfers occur on the PDATA0 (J2-3) through PDATA7 (J2-10) bus. This
PDATA bus is pulled down through resistors on the LCU CCA. The RMS is considered the master and the LCU is
considered the slave.
Analog multiplexor U52 switches Ident signals FFM1_IDENT (J1-3), FFM2_IDENT (J1-22) MKR1_IDENT (J3-5), and
MKR2_IDENT (J4-5) through to R86, R85, and C134 under control of latch U53. Resistor R86 and R85 divide the Ident
tone to audio input levels before feeding audio amplifier U27 through coupling capacitor C134. Each Ident tone can be
individually switched through the U52 multiplexor as well as DGND; which will not have an audio tone (Ident mute).
FFM TX Disable header JP2 will normally not connect the FFM1 or FFM2 TX to J1-1 or J1-20 to prevent interference with
a direct-connected Far Field Monitor. This option header may be used differently in future designs.