User's Manual

MODEL 2130 MARKER BEACON
2-4 Rev. A April, 2005
This document contains proprietary information and such information may not be disclosed to others for any
purposes without written permission from SELEX Sistemi Integrati Inc.
2.3.1.2 Marker Beacon Amplifier/ Monitor Detailed Circuit Theory
2.3.1.2.1 Power Supply
Refer to Figure 11-12 Sheet 2. The power for the Amplifier/Monitor enters on J3 pins 21, 22, and 23. The 12 volts is
converted to 5 VDC by DC-DC Converter PS1. The output of PS1 enters U19, a linear voltage converter that drops the
voltage to 3.3 VDC and is labeled DVCC for use as the digital supply voltage.
The 12 VDC also enters U20 where it is converted by a linear converter to +5 VDC and labeled VCC. This voltage powers
the TXCO, U5.
The 12 VDC is converted to +5 VDC by U16. This 5 VDC is used by RF amplifiers U17 and U18 as the supply voltage for
operation. Separate power supplies are used to provide noise immunity from one function of the amplifier to another.
2.3.1.2.2 Synthesizer
Refer to Figure 11-12 sheet 2. Integrated circuit U13 acts as the loop controller for the synthesizer circuit. Microprocessor
U8 sets the channel information into U13 by serial shifting data into the circuit. Data enters on the line marked
Synth_data. The data is clocked into the circuit by Synth_clock. When programming is complete Synth_LE is toggled.
The signal Synth_lock when low indicates that the synthesizer is locked on frequency.
The loop filter is comprised of C54, R22, C56, R21 and C58. The output of the loop filter controls the VCO. The voltage
into the tune input sets the output frequency of the VCO U15. Power for the VCO enters on J3 pin 20. This voltage
originates on the LCU and is one of the duplicated methods to disable the transmitter. The VCO power is regulated to 10
volts DC by low voltage drop regulator U14. The output of U14 is filtered by caps C57, C113, and C62 and enters the VCO
U15.
The output of the VCO is attenuated by R29, R30 and R32 and amplified by U17. The output of U17 is split in two by R34,
R37 and R35 resulting in a 6 dB power loss. The combination of R35, R36 and R28 forms another attenuator prior to
entering the VCO controller U13 where the signal is divided, compared against the reference frequency and the VCO
control voltage corrected.
The other output of the power divider formed by R34, R35 and R37 enters U18 and amplified. Resistors R42, R43 and R46
form an attenuator prior to entering U21. U21 amplifies the signal and provides an output level of approximately 10 mW
and is marked PA_DRIVE.
Refer to Figure 11-12 sheet 4. The modulation for the RF amplifiers originates from U8 microprocessor. Serial data is
transferred to D/A converter U37. The signal from U37 is low pass filtered by U24B and U24C. Op Amp U24A combines
the detected signal from U26A and U24A with the modulation from U24C. U24A drives FETs Q4, Q5 and Q10 as a class A
Modulator. Op Amp U30D takes the detected signal and amplifies to TTL level for monitoring.
FET Q2 is the first amplifier stage that provides approximately 10 dB of gain. The input from the frequency synthesizer
section enters at PA_DRIVE. The modulation enters through R51 and L13. The gate bias voltage enters through R52. The
gate voltage is set by potentiometer R54 and R53 and derived from a precise voltage set by R55 and zener diode CR7.
Capacitors C99 and C101 filter this 7.5 VDC to eliminate noise.