User's Manual

MODEL 2130 MARKER BEACON
2-2 Rev. A April, 2005
This document contains proprietary information and such information may not be disclosed to others for any
purposes without written permission from SELEX Sistemi Integrati Inc.
2.3.1.1 Marker Beacon Amplifier/ Monitor Block Diagram Theory
Refer to Figure 2-1. The Amplifier/Monitor includes a frequency synthesizer that can be programmed to 75 MHz. In
addition the frequency can be set to 4 kHz higher or 4 kHz lower than 75 MHz. The synthesizer channel is set from the
PMDT interface.
The output of the synthesizer is amplified in two stages to obtain 2.5 Watts. A low pass filter in the output rejects
harmonics and high frequency spurious signals. The low pass filter is followed by a directional coupler for monitoring
forward and reverse power. A jumper selectable 6 dB attenuator allows for the amplifier to operate down to the lower
power level of the Inner Marker Beacon.
The RF amplifier is modulated class A.
The directional coupler forward and reverse power signals are fed back into an IF detector and into an A/D converter for
measurement. In addition the monitor return from the antenna and the standby transmitter signal from the LCU transfer
logic is fed into the detector and the A/D converter for processing.
The microprocessor is an Analog Devices Blackfin, BF532. This is a 16 bit processor running at 400 MHz internally. This
is possible by an internal phase locked loop. Flash memory is provided to store program information A non-volatile
memory that provides long term storage of setup information is used along with a real-time clock crystal in conjunction
with the internal used to provide day/date/time information.
Setup information is provided to the Amplifier/ Monitor through the serial communications channel to the RMS CCA. The
RMS communicates to the PMDT and any setup information is passed to the Amplifier/ Monitor from the RMS.
Figure 2-1 Amplifier/Monitor Block Diagram