C200H Programmable Controllers (CPU01-E/03-E/11-E) Operation Manual Revised June 2003
Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury to people or damage to property. DANGER Indicates an imminently hazardous situation which, if not avoided, will result in death or serious injury.
TABLE OF CONTENTS PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TABLE OF CONTENTS SECTION 5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TABLE OF CONTENTS Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About this Manual: The OMRON C200H PCs offer a simple but effective way to automate processing. Manufacturing, assembly, packaging, and many other processes can be automated to save time and money. This manual describes the characteristics and abilities of the PCs, as well as programming operations and instructions and other aspects of operation and preparation. Before attempting to operate the PC, thoroughly familiarize yourself with the information contained herein.
PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the Programmable Controller. You must read this section and understand the information contained before attempting to set up or operate a PC system. 1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Safety Precautions 1 Intended Audience This manual is intended for the following personnel, who must also have knowledge of electrical systems (an electrical engineer or the equivalent). • Personnel in charge of installing FA systems. • Personnel in charge of designing FA systems. • Personnel in charge of managing FA systems and facilities. 2 General Precautions The user must operate the product according to the performance specifications described in the relevant manuals.
5 Application Precautions • The PC outputs may remain ON or OFF due to deposition or burning of the output relays or destruction of the output transistors. As a countermeasure for such problems, external safety measures must be provided to ensure safety in the system. • When the 24-VDC output (service power supply to the PC) is overloaded or short-circuited, the voltage may drop and result in the outputs being turned OFF.
Application Precautions ! Caution 5 Failure to abide by the following precautions could lead to faulty operation of the PC or the system, or could damage the PC or PC Units. Always heed these precautions. • Fail-safe measures must be taken by the customer to ensure safety in the event of incorrect, missing, or abnormal signals caused by broken signal lines, momentary power interruptions, or other causes. • Interlock circuits, limit circuits, and similar safety measures in external circuits (i.e.
Application Precautions 5 • When replacing parts, be sure to confirm that the rating of a new part is correct. Not doing so may result in malfunction or burning. • Before touching a Unit, be sure to first touch a grounded metallic object in order to discharge any static built-up. Not doing so may result in malfunction or damage.
SECTION 1 Introduction This section gives a brief overview of the history of Programmable Controllers and explains terms commonly used in ladder-diagram programming. It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the C200H, and a table of other manuals available to use with this manual for special PC applications, are also provided. 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 Overview . . . .
Section 1-2 The Origins of PC Logic 1-1 Overview A PC (Programmable Controller) is basically a CPU (Central Processing Unit) containing a program and connected to input and output (I/O) devices. The program controls the PC so that when an input signal from an input device turns ON, the appropriate response is made. The response normally involves turning ON an output signal to some sort of output device.
Section 1-3 PC Terminology Actually there is not a total equivalence between these terms. The term condition is only used to describe ladder diagram programs in general and is specifically equivalent to one of certain set of basic instructions. The terms input and output are not used in programming per se, except in reference to I/O bits that are assigned to input and output signals coming into and leaving the PC.
Section 1-5 Overview of PC Operation 1-4 OMRON Product Terminology OMRON products are divided into several functional groups that have generic names. Appendix A Standard Models list products according to these groups. The term Unit is used to refer to all of the OMRON PC products. Although a Unit is any one of the building blocks that goes together to form a C200H PC, its meaning is generally, but not always, limited in context to refer to the Units that are mounted to a Rack.
Section 1-6 Peripheral Devices 8. 9. Guide and to Operation Manuals and System Manuals for details on individual Units. Test the program in an actual control situation and carry out fine tuning as required. (Section 7 Program Monitoring and Execution and Section 8 Troubleshooting) Record two copies of the finished program on masters and store them safely in different locations.
Peripheral Devices Programming Console Section 1-6 A Programming Console is the simplest form of programming device for OMRON PCs. Although a Programming Console Adapter is sometimes required, all Programming Consoles are connected directly to the CPU without requiring a separate interface. The Programming Console also functions as an interface to transfer programs to a standard cassette tape recorder. Various types of Programming Console are available, including both CPU-mounting and Hand-held models.
Section 1-7 Available Manuals 1-7 Available Manuals The following table lists other manuals that may be required to program and/ or operate the C200H. Operation Manuals and/or Operation Guides are also provided with individual Units and are required for wiring and other specifications. Name Cat. No.
Section 1-8 LSS Capabilities Name Cat. No. Contents Heat/Cool Temperature Control Unit Operation Manual W240 Information on Heating and Cooling Temperature Control Unit PID Control Unit Operation Manual W241 Information on PID Control Unit Cam Positioner Unit Operation Manual W224 Information on Cam Positioner Unit 1-8 LSS Capabilities The LSS is a complete programming and control package designed for C-series PCs.
Section 1-8 LSS Capabilities Group Description DM (data memory) DM operations are used to edit DM data in hexadecimal or ASCII form. There are also features for copying, filling and printing DM data, as well as data disk save and retrieve operations. I/O TABLE I/O TABLE is used to edit, check, and print I/O tables. It also provides data disk save and retrieve operations. UTILITY DATA AREA LISTS Displays lists of such items as used areas and cross-references (i.e.
Section 1-8 LSS Capabilities 1-8-3 Offline and Online Operations Group Description SYSTEM SETUP The SYSTEM SETUP provides settings for the operating environment of the LSS, including the PC that’s being communicated with (including network and interface settings) and disk drive, comment, printer, PROM Writer, and monitor settings. It also provides settings for transfer of I/O table and data link tables to UM.
SECTION 2 Hardware Considerations This section provides information on hardware aspects of the C200H that are relevant to programming and software operation. These include indicators on the CPU Unit and basic PC configuration. This information is covered in detail in the C200H Installation Guide. 2-1 2-2 Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 2-2 PC Configuration 2-1 Indicators CPU indicators provide visual information on the general operation of the PC. Although not substitutes for proper error programming using the flags and other error indicators provided in the data areas of memory, these indicators provide ready confirmation of proper operation. CPU Indicators CPU indicators are shown below and are described in the following table. Indicator Function POWER Lights when power is supplied to the CPU.
PC Configuration Section 2-2 onto an Expansion I/O Backplane to which a Power Supply and up to eight other Units are mounted. An Expansion I/O Rack is always connected to the CPU via the connectors on the Backplanes, allowing communication between the two Racks. Up to two Expansion I/O Racks can be connected in series to the CPU Rack. Unit Mounting Position Only I/O Units and Special I/O Units can be mounted to Slave Racks.
SECTION 3 Memory Areas Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a different function. The areas generally accessible by the user for use in programming are classified as data areas. The other memory area is the Program Memory, where the user’s program is actually stored.
Section 3-2 Data Area Structure 3-1 Introduction Details, including the name, acronym, range, and function of each area are summarized in the following table. All but the last three of these areas are data areas. Data and memory areas are normally referred to by their acronyms. Area Acronym Range Function Internal Relay IR Words: 000 to 235 Bits: 00000 to 23515 Used to control I/O points, other bits, timers, and counters, and to temporarily store data.
Section 3-2 Data Area Structure and not entered, when programming. Any data area designation without an acronym is assumed to be in either the IR or SR area. Because IR and SR addresses run consecutively, the word or bit addresses are sufficient to differentiate these two areas. An actual data location within any data area but the TC area is designated by its address. The address designates the bit or word within the area where the desired data is located.
Section 3-3 IR Area tains four digits, which are numbered from right to left. These digit numbers and the corresponding bit numbers for one word are shown below. Digit number Bit number Contents 3 2 1 0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When referring to the entire word, the digit numbered 0 is called the rightmost digit; the one numbered 3, the leftmost digit.
Section 3-3 IR Area signed as I/O bits can be used as work bits. IR area work bits are reset when power is interrupted or PC operation is stopped. I/O Words If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the Unit sends an output from the PC, the bit is an output bit. To turn on an output, the output bit assigned to it must be turned ON. When an input turns on, the input bit assigned to it also turns ON.
Section 3-4 SR Area two Masters are used. IR area words are allocated to Special I/O Units and Slave Racks by the unit number on the unit, as shown in the following tables.
Section 3-4 SR Area turns one ON then OFF, the specified Link Unit will be restarted. Other control bits are OFF until set by the user.
Section 3-4 SR Area Word(s) 253 254 255 3-4-1 Bit(s) Function 00 to 07 FAL number output area. 08 Low Battery Flag 09 Cycle Time Error Flag 10 I/O Verification Error Flag 11 Host Computer to rack-mounting Host Link Unit Level 0 Error Flag 12 Remote I/O Error Flag 13 Normally ON Flag 14 Normally OFF Flag 15 First cycle 00 1-minute clock pulse bit 01 0.02-second clock pulse bit 02 to 06 Reserved for function expansion. Do not use.
Section 3-4 SR Area If the content of bits 12 through 15 is B, an error has occurred in a Remote I/O Master or Slave Unit, and the content of bits 08 through 11 will indicate the unit number, either 0 or 1, of the Master involved. In this case, bits 04 to 06 contain the unit number of the Slave Rack involved. If the content of bits 12 through 15 is a number from 0 to 31, an error has occurred in an Optical I/O Unit.
Section 3-4 SR Area SYSMAC NET Link Loop Status Output SR 236 contains the SYSMAC NET Link Loop Status Flags. Bits 00 through 07 are the Loop Status Flags for operating level 0, and bits 08 through 15 are the Flags for operating level 1. The bit functions are shown below. Level 0: Level 1: 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 1 1 1 1 Central Power Supply Unit: 0: Power supply connected. 1: Power supply not connected.
Section 3-4 SR Area SYSMAC NET Link Systems Completion code Name Meaning 00 Normal end Data transfer was completed successfully. 01 Parameter error SEND(90)/RECV(98) instruction operands are not within specified ranges. 02 Transmission impossible The System was reset during execution of the instruction or the destination node is not in the System. 03 Busy error The destination node is busy and cannot receive the transfer. 04 Transmission error The line server token was not received.
Section 3-4 SR Area tem in operating level 0; the other half, in a Subsystem in operating level 1. The actual bit assignments depend on whether the PC is in a Single-level PC Link System or a Multilevel PC Link System. Refer to the PC Link System Manual for details. Error and Run Flag bit assignments are described below. Bits 00 through 07 of each word are the Run flags, which are ON when the PC Link Unit is in RUN mode.
Section 3-4 SR Area Multilevel PC Link Systems Flag type Run flags Error flags Application Example 3-4-3 Bit no.
Section 3-4 SR Area SR 25211 is not effective when switching to RUN mode. SR 25211 should be manipulated from a Peripheral Device, e.g., a Programming Console or FIT. Maintaining Status during Startup The status of SR 25211 and thus the status of force-set/force-reset bits can be maintained when power is turned off and on by inserting the Set System instruction (SYS(49)) in the program as step 00000 with the proper operand.
Section 3-4 SR Area Operating without a Battery In the following cases, DM (DM 0000 to DM 0999), HR, AR, CNT, and SR area data will not be retained in the CPU Unit’s internal RAM when the power is turned OFF. • When a RAM Unit without battery backup is used and the backup time has been exceeded for the backup capacitor. • When a RAM Unit with battery backup is used, but the battery is low.
Section 3-4 SR Area 3-4-6 FAL (Failure Alarm) Area A 2-digit BCD FAL code is output to bits 25300 to 25307 when the FAL or FALS instruction is executed. These codes are user defined for use in error diagnosis, although the PC also outputs FAL codes to these bits, such as one caused by battery voltage drop. This area can be reset by executing the FAL instruction with an operand of 00 or by performing a Failure Read Operation from the Programming Console.
Section 3-4 SR Area Bit 25400 1-min clock pulse 30 s 30 s Bit 25401 0.02-s clock pulse .01 s 1 min. .02 s Bit 25500 0.1-s clock pulse .05 s .05 s 0.1 s 0.5 s 1.0 s 3-4-12 Bit 25501 0.2-s clock pulse 0.1 s 0.1 s 0.2 s Bit 25502 1.0-s clock pulse 0.5 s .01 s Caution: Because the 0.1-second and 0.02-second clock pulse bits have ON times of 50 and 10 ms, respectively, the CPU may not be able to accurately read the pulses if program execution time is too long.
Section 3-5 AR Area 3-5 AR (Auxiliary Relay) Area AR word addresses extend from AR 00 to AR 27; AR bit addresses extend from AR 0000 to AR 2715. Most AR area words and bits are dedicated to specific uses, such as transmission counters, flags, and control bits, and words AR 00 through AR 06 and AR 23 through AR 27 cannot be used for any other purpose. Words and bits from AR 07 to AR 22 are available as work words and work bits if not used for the following assigned purposes.
Section 3-5 AR Area Word(s) Bit(s) Function 12 to 15 00 to 15 Active Node Flags for SYSMAC LINK System nodes of operating level 1 16 00 to 15 SYSMAC LINK/SYSMAC NET Link System operating level 0 service time per cycle 17 00 to 15 SYSMAC LINK/SYSMAC NET Link System operating level 1 service time per cycle 18 to 21 00 to 15 Calendar/clock Area (CPU11-E only) 22 00 to 15 TERMINAL Mode Key Bits (CPU11-E only) 23 00 to 15 Power Off Counter 24 00 to 03 Not used.
Section 3-5 AR Area 3-5-2 SYSMAC LINK System Data Link Settings AR 0700 to AR 0703 and AR 0704 to AR 0707 are used to designate word allocations for operating levels 0 and 1 of the SYSMAC LINK System. Allocation can be set to occur either according to settings from an FIT or automatically in the LR and/or DM areas. If automatic allocation is designated, the number of words to be allocated to each node is also designated. These settings are shown below.
Section 3-5 AR Area Level 0 Level 1 Bit (body of table shows node numbers) 00 01 02 03 04 05 09 10 AR 08 AR 12 1 2 3 4 5 6 7 06 8 07 9 08 10 11 12 11 13 12 14 13 15 14 16 15 AR 09 AR 13 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AR 10 AR 14 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 AR 11 AR 15 49 50 51 52 53 54 55 56 57 58 59 60 61 62 * ** *Communication Controller Error Flag **EEPROM Error Flag 3-5-5 SYS
Section 3-5 AR Area 1, 2, 3... 1. 2. Turn ON AR 2114 (Stop Bit). Set the desired date, day, and time, being careful not to turn OFF AR 2114 (Stop Bit) when setting the day of the week (they’re in the same word). (On the Programming Console, the Bit/Digit Monitor and Force Set/Reset Operations are the easiest ways to set this data.) Note A more convenient way is if steps 1 and 2 are executed simultaneously as follows. Set 4000 to 4006 with present value change. Stop bit ON data 3.
Section 3-5 AR Area 3-5-9 CPU Low Battery Flag (CPU11-E Only) AR 2404 is the Battery Alarm Flag for the CPU11-E backup battery. AR 2404 is refreshed every cycle while the PC is in RUN or MONITOR mode. 3-5-10 SCAN(18) Cycle Time Flag (CPU11-E Only) AR 2405 turns ON when the cycle time set with SCAN(18) is shorter than the actual cycle time. AR 2405 is refreshed every cycle while the PC is in RUN or MONITOR mode.
Section 3-6 DM Area 3-6 DM (Data Memory) Area The DM area is divided into various parts as described in the following table. Addresses User read/write Usage DM 0000 to DM 0968 Read/write General User Area DM 0969 to DM 0999 Read/write Error History Area (CPU11-E only) DM 1000 to DM 1999 Read only Special I/O Unit Data Area Although composed of 16-bit words like any other data area, all data in any part of the DM area cannot be specified by bit for use in instructions with bit operands.
Section 3-6 DM Area Area Structure Error records occupy three words each stored between DM 0970 and DM 0999. The last record that was stored can be obtained via the content of DM 0969 (Error Record Pointer). The record number, DM words, and pointer value for each of the ten records are as follows: Record Addresses Pointer value None N.A.
Section 3-8 TC Area to 0000, the Error History Area will be reset (i.e., cleared), and any further error codes will be recorded from the beginning of the Error History Area. AR 0715 (Error History Enable Bit) must be ON to reset the Error History Area. Special I/O Unit Data The DM area between 1000 and 1999 is allocated to Special I/O Units as shown below. When not used for this purpose, this area is available for other uses.
Section 3-9 LR Area Once defined, a TC number can be designated as an operand in one or more of certain set of instructions other than those listed above. When defined as a timer, a TC number designated as an operand takes a TIM prefix. The TIM prefix is used regardless of the timer instruction that was used to define the timer. Once defined as a counter, the TC number designated as an operand takes a CNT prefix.
Section 3-11 TR Area 3-10 Program Memory Program Memory is where the user program is stored. The amount of Program Memory available is either 4K or 8K words, depending on the type of Memory Unit mounted to the CPU. Memory Units come in different types, such as RAM and ROM Units, and for each type there are different sizes. (Refer to the Installation Guide for details.
SECTION 4 Writing and Inputting the Program This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the program into memory, and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution. The entire set of instructions used in programming is described in Section 5 Instruction Set. 4-1 4-2 4-3 Basic Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 4-2 Instruction Terminology 4-1 Basic Procedure There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix F Word Assignment Recording Sheets and Appendix G Program Coding Sheet. 1, 2, 3... 1. Obtain a list of all I/O devices and the I/O points that have been assigned to them and prepare a table that shows the I/O bit allocated to each I/O device. 2.
Section 4-3 Basic Ladder Diagrams designated as an operand is called an operand word. If the actual value is entered as a constant, it is preceded by # to indicate that it is not an address. Other terms used in describing instructions are introduced in Section 5 Instruction Set. 4-3 Basic Ladder Diagrams A ladder diagram consists of one line running down the left side with lines branching off to the right. The line on the left is called the bus bar; the branching lines, instruction lines or rungs.
Section 4-3 Basic Ladder Diagrams something to happen when a bit is ON, and a normally closed condition when you want something to happen when a bit is OFF. 00000 Instruction Instruction is executed when IR bit 00000 is ON. Instruction Instruction is executed when IR bit 00000 is OFF.
Section 4-3 Basic Ladder Diagrams structions require no operands, while others require up to three operands, Program Memory addresses can be from one to four words long. Program Memory addresses start at 00000 and run until the capacity of Program Memory has been exhausted. The first word at each address defines the instruction. Any definers used by the instruction are also contained in the first word.
Section 4-3 Basic Ladder Diagrams quires one line of mnemonic code. “Instruction” is used as a dummy instruction in the following examples and could be any of the right-hand instructions described later in this manual. 00000 A LOAD instruction. 00000 A LOAD NOT instruction.
Section 4-3 Basic Ladder Diagrams (in order from the top) to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of these instructions requires one line of mnemonic code. 00000 Instruction 00100 LR 0000 Address Instruction 00000 00001 00002 00003 LD OR NOT OR Instruction Operands LR 00000 00100 0000 The instruction will have an ON execution condition when any one of the three conditions is ON, i.e., when IR 00000 is OFF, when IR 00100 is OFF, or when LR 0000 is ON.
Section 4-3 Basic Ladder Diagrams tion, and that’s where AND LOAD and OR LOAD instructions are used. Before we consider more complicated diagrams, however, we’ll look at the instructions required to complete a simple “input-output” program. 4-3-4 OUTPUT and OUTPUT NOT The simplest way to output the results of combining execution conditions is to output it directly with the OUTPUT and OUTPUT NOT.
Section 4-3 Basic Ladder Diagrams described later. The END instruction requires no operands and no conditions can be placed on the same instruction line with it. 00000 00001 Instruction END(01) Address Instruction 00000 00001 00002 00003 LD AND NOT Instruction END(01) Program execution ends here. Operands 00000 00001 --- If there is no END instruction anywhere in the program, the program will not be executed at all.
Section 4-3 Basic Ladder Diagrams OR NOT between just IR 00003 and the result of an AND between IR 00002 and the first OR. What we need is a way to do the OR (NOT)’s independently and then combine the results. To do this, we can use the LOAD or LOAD NOT instruction in the middle of an instruction line. When LOAD or LOAD NOT is executed in this way, the current execution condition is saved in a special buffer and the logic process is restarted.
Section 4-3 Basic Ladder Diagrams blocks to be combined, starting each block with LOAD or LOAD NOT, and then to code the logic block instructions which combine them. In this case, the instructions for the last pair of blocks should be combined first, and then each preceding block should be combined, working progressively back to the first block.
Section 4-3 Basic Ladder Diagrams or the three blocks can be coded first followed by two OR LOADs. The mnemonic codes for both methods are shown below.
Section 4-3 Basic Ladder Diagrams lowed by the one to combine the execution condition resulting from the first logic block instruction and the execution condition of the logic block third from the end, and on back to the first logic block that is being combined.
Section 4-3 Basic Ladder Diagrams blocks a and b would be combined using AND LOAD as shown above, and then block c would be coded and a second AND LOAD would be used to combined it with the execution condition from the first AND LOAD. Then block d would be coded, a third AND LOAD would be used to combine the execution condition from block d with the execution condition from the second AND LOAD, and so on through to block n.
Section 4-3 Basic Ladder Diagrams last two blocks and working backward. The OR LOAD at program address 00008 combines blocks blocks d and e, the following AND LOAD combines the resulting execution condition with that of block c, etc.
Section 4-4 The Programming Console tion condition of block c with the execution condition resulting from the normally closed condition assigned IR 00003. The rest of the diagram can be coded with OR, AND, and AND NOT instructions. The logical flow for this and the resulting code are shown below.
Section 4-4 The Programming Console gramming Console and the operation necessary to prepare for program input. 4-6 Inputting, Modifying, and Checking the Program describes actual procedures for inputting the program into memory. Depending on the model of Programming Console used, it is either connected to the CPU via a Programming Console Adapter and Connecting Cable or it is mounted directly to the CPU.
Section 4-4 The Programming Console The gray keys other than the SHIFT key have either the mnemonic name of the instruction or the abbreviation of the data area written on them. The functions of these keys are described below. Pressed before the function code when inputting an instruction via its function code. Pressed to enter SFT (the Shift Register instruction).
Section 4-4 The Programming Console operation as well as the procedures that are possible from the Programming Console. RUN mode is the mode used for normal program execution. When the switch is set to RUN and the START input on the CPU Power Supply Unit is ON, the CPU will begin executing the program according to the program written in its Program Memory. Although monitoring PC operation from the Programming Console is possible in RUN mode, no data in any of the memory areas can be input or changed.
Section 4-5 Preparation for Operation The mode will not change when a peripheral device is removed from the PC after PC power is turned on. DANGER! Always confirm that the Programming Console is in PROGRAM mode when turning on the PC with a Programming Console connected unless another mode is desired for a specific purpose. If the Programming Console is in RUN mode when PC power is turned on, any program in Program Memory will be executed, possibly causing a PC-controlled system to begin operation.
Section 4-5 Preparation for Operation The PC prompts you for a password when PC power is turned on or, if PC power is already on, after the Programming Console has been connected to the PC. To gain access to the system when the “Password!” message appears, press CLR and then MONTR. Then press CLR to clear the display. If the Programming Console is connected to the PC when PC power is already on, the first display below will indicate the mode the PC was in before the Programming Console was connected.
Section 4-5 Preparation for Operation Key Sequence Program Memory cleared from designated address. Both AR and HR areas TC area Retained if pressed DM area All Clear The following procedure is used to clear memory completely.
Section 4-5 Preparation for Operation To leave the TC area uncleared and retaining Program Memory addresses 00000 through 00122, input as follows: 00000 00000 00000 00000MEM CLR ? HR CNT DM 00000MEM CLR ? HR DM 00123MEM CLR ? HR DM 00000MEM CLR END HR DM 4-5-4 Registering the I/O Table The I/O Table Registration operation writes the types of I/O Units controlled by the PC and the Rack locations of the I/O Units into the I/O table memory area of the CPU (see Section 3-3 IR Area).
Section 4-5 Preparation for Operation Initial I/O Table Registration Memory cleared completely 00000 00000 FUN (??) 00000I/OTBL? ?Ć?U= 00000I/OTBL WRIT ???? Register I/O table 00000I/OTBL WRIT 9713 00000I/OTBL WRIT OK 4-5-5 Clearing Error Messages After the I/O table has been registered, any error messages recorded in memory should be cleared. It is assumed here that the causes of any of the errors for which error messages appear have already been taken care of.
Section 4-5 Preparation for Operation Example 00000 00000 FUN (??) 00000I/OTBL? ?Ć?U= 00000I/OTBL OK VER 00000I/OTBL VER 0Ć1U=O*** I*** (No errors) (An error occurred) Actual I/O words Registered I/O table words I/O slot number Rack number Meaning of Displays 00000I/OTBL VER **=R*ĆI R*ĆW Duplication 00000I/OTBL VER *Ć*U=**** RMT* Indicates a Remote I/O Unit that has not been registered 4-5-7 Reading the I/O Table The I/O Table Read operation is used to access the I/O table that is currently regi
Section 4-5 Preparation for Operation Example 00000 00000 FUN (??) 00000I/OTBL ? ?Ć?U= (PC Unit) (Slave Rack Units) 00000I/OTBL ? R??Ć?U= (Optical I/O Unit) 00000I/OTBL ? 2??LU= 00000I/OTBL ? 0Ć?U= 00000I/OTBL ? 0Ć5U= 00000I/OTBL READ 0Ć5U=i*** 005 00000I/OTBL READ 0Ć4U=o*** 004 00000I/OTBL READ 0Ć5U=i*** 005 Meaning of Displays: I/O Unit Designations for Displays (see I/O Units Mounted in Remote Slave Racks, next page) C500, 1000H/C2000H I/O Units No.
Section 4-5 Preparation for Operation I/O Units 00000I/OTBL READ *Ć*U=**** *** I/O word number I/O type: i: (input), o: (output) Unit number (0 to 9) Rack number (0 to 2) Special I/O Units 00000I/OTBL READ *Ć*U=$*** Blank: W: Unit 1 exclusively Unit 2 exclusively C: High-speed Counter Special I/O N: Host Link Unit Unit type: A: Other Unit number (0 to 9) Indicates Special I/O Unit Remote I/O Master Units 00000I/OTBL READ *Ć*U=RMT* Remote I/O Master no.
Section 4-5 Preparation for Operation tion based on the I/O Units mounted when the I/O Table Clear operation is performed. The I/O Table Clear operation will reset all Special I/O Units and Link Units mounted at the time. Do not perform the I/O Table Clear operation when a Host or PC Link Unit, Remote I/O Master Unit, High-speed Counter Unit, Position Control Unit, or other Special I/O Unit is in operation.
Section 4-5 Preparation for Operation Key Sequence Example 00000 00000 FUN(??) 00000LINK TBL~UM (SYSMACĆNET)???? 00000LINK TBL~UM (SYSMACĆNET)9713 00000LINK TBL~UM OK The following indicates that the I/O table cannot be transferred.
Inputting, Modifying, and Checking the Program 4-6 Section 4-6 Inputting, Modifying, and Checking the Program Once a program is written in mnemonic code, it can be input directly into the PC from a Programming Console. Mnemonic code is keyed into Program Memory addresses from the Programming Console. Checking the program involves a syntax check to see that the program has been written according to syntax rules.
Section 4-6 Inputting, Modifying, and Checking the Program Example If the following mnemonic code has already been input into Program Memory, the key inputs below would produce the displays shown.
Section 4-6 Inputting, Modifying, and Checking the Program Inputting SV for Counters and Timers The SV (set value) for a timer or counter is generally entered as a constant, although inputting the address of a word that holds the SV is also possible. When inputting an SV as a constant, CONT/# is not required; just input the numeric value and press WRITE. To designate a word, press CLR and then input the word address as described above.
Section 4-6 Inputting, Modifying, and Checking the Program Example The following program can be entered using the key inputs shown below. Displays will appear as indicated.
Section 4-6 Inputting, Modifying, and Checking the Program the displays shown below will be replaced with numeric data, normally an address, in the actual display. Message Cause and correction ****REPL ROM An attempt was made to write to ROM, or to write-protected RAM or EEPROM. Ensure that a RAM or EEPROM Unit is mounted and that its write-protect switch is set to OFF. ****PROG OVER The instruction at the last address in memory is not NOP(00).
Section 4-6 Inputting, Modifying, and Checking the Program Many of the following errors are for instructions that have not yet been described yet. Refer to 4-7 Controlling Bit Status or to Section 5 Instruction Set for details on these. Type Type A Type B Type C Message Meaning and appropriate response ????? The program has been lost. Re-enter the program. NO END INSTR There is no END(01) in the program. Write END(01) at the final address in the program.
Section 4-6 Inputting, Modifying, and Checking the Program Example The following example shows some of the displays that can appear as a result of a program check. 00000 00000PROG CHK CHKLEVEL (0Ć2)? 00064PROG CHK Display #1 Halts program check 00128PROG CHKEND Display #2 Check continues until END(01) 03000PROG CHK END (01)(03.
Inputting, Modifying, and Checking the Program Section 4-6 Example 00000 00000CYCLE TIME 054.1MS 00000CYCLE TIME 053.9MS 4-6-5 Program Searches The program can be searched for occurrences of any designated instruction or data area address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display. To designate a bit address, press SHIFT, press CONT/#, then input the address, including any data area designation required, and press SRCH.
Section 4-6 Inputting, Modifying, and Checking the Program Example: Instruction Search 00000 00000 LD 00000 00200SRCH LD 00000 00202 LD 00000 06000SRCH END (01)(06.4KW) 00000 00100 00100 TIM 001 00203SRCH TIM 001 00203 TIM DATA #0123 Example: Bit Search 00000 00000CONT SRCH CONT 00005 00200CONT SRCH LD 00005 00203CONT SRCH AND 00005 06000 END (01)(06.
Section 4-6 Inputting, Modifying, and Checking the Program words are required for the instruction, input these in the same way as when inputting the program initially. To delete an instruction, display the instruction word of the instruction to be deleted and then press DEL and the up key. All the words for the designated instruction will be deleted. Caution Be careful not to inadvertently delete instructions; there is no way to recover them without reinputting them completely.
Section 4-6 Inputting, Modifying, and Checking the Program Inserting an Instruction 00000 00000 OUT 00000 00000 OUT 00201 00207SRCH OUT 00201 00206READ AND NOT 00104 00206 AND 00000 00206 AND 00105 Find the address prior to the insertion point Program After Insertion Address Instruction 00000 00001 00002 00003 00004 00005 00006 00007 00008 00009 LD AND LD AND NOT OR LD AND AND AND NOT OUT END(01) Operands 00100 00101 00201 00102 00103 00105 00104 00201 - 00206INSERT? AND 00105 00207INSERT
Section 4-6 Inputting, Modifying, and Checking the Program 4-6-7 Branching Instruction Lines When an instruction line branches into two or more lines, it is sometimes necessary to use either interlocks or TR bits to maintain the execution condition that existed at a branching point. This is because instruction lines are executed across to a right-hand instruction before returning to the branching point to execute instructions on a branch line.
Section 4-6 Inputting, Modifying, and Checking the Program This execution condition is then restored after executing the right-hand instruction by using the same TR bit as the operand of a LOAD instruction TR 0 Address 00001 00000 Instruction 1 00002 Instruction 2 Diagram B: Corrected Using a TR bit 00000 00001 00002 00003 00004 00005 00006 Instruction Operands LD OUT AND Instruction 1 LD AND Instruction 2 00000 0 00001 TR TR 0 00002 In terms of actual instructions the above diagram would be
Section 4-6 Inputting, Modifying, and Checking the Program and ease of understanding a program increased by redrawing a diagram that would otherwise required TR bits. In both of the following pairs of diagrams, the bottom versions require fewer instructions and do not require TR bits.
Section 4-6 Inputting, Modifying, and Checking the Program (ILC(03)) instructions to eliminate the branching point completely while allowing a specific execution condition to control a group of instructions. The INTERLOCK and INTERLOCK CLEAR instructions are always used together. When an INTERLOCK instruction is placed before a section of a ladder program, the execution condition for the INTERLOCK instruction will control the execution of all instruction up to the next INTERLOCK CLEAR instruction.
Section 4-6 Inputting, Modifying, and Checking the Program As shown in the following diagram, more than one INTERLOCK instruction can be used within one instruction block; each is effective through the next INTERLOCK CLEAR instruction.
Section 4-6 Inputting, Modifying, and Checking the Program did not exist. Diagram B from the TR bit and interlock example could be redrawn as shown below using a jump. Although 01 has been used as the jump number, any number between 01 and 99 could be used as long as it has not already been used in a different part of the program. JUMP and JUMP END require no other operand and JUMP END never has conditions on the instruction line leading to it.
Section 4-7 Controlling Bit Status 4-7 Controlling Bit Status There are five instructions that can be used generally to control individual bit status. These are the OUTPUT, OUTPUT NOT, DIFFERENTIATE UP, DIFFERENTIATE DOWN, and KEEP instructions. All of these instructions appear as the last instruction in an instruction line and take a bit address for an operand.
Section 4-8 Work Bits one instruction line, the instruction lines are coded first before the instruction that they control.
Section 4-8 Work Bits Work Bit Applications Examples given later in this subsection show two of the most common ways to employ work bits. These should act as a guide to the almost limitless number of ways in which the work bits can be used. Whenever difficulties arise in programming a control action, consideration should be given to work bits and how they might be used to simplify programming.
Section 4-9 Programming Precautions ple, IR 00100 must be left ON continuously as long as IR 00001 is ON and both IR 00002 and IR 00003 are OFF, or as long as IR 00004 is ON and IR 00005 is OFF. It must be turned ON for only one cycle each time IR 00000 turns ON (unless one of the preceding conditions is keeping it ON continuously). This action is easily programmed by using IR 22500 as a work bit as the operand of the DIFFERENTIATE UP instruction (DIFU(13)).
Section 4-9 Programming Precautions The number of times any particular bit can be assigned to conditions is not limited, so use them as many times as required to simplify your program. Often, complicated programs are the result of attempts to reduce the number of times a bit is used. Except for instructions for which conditions are not allowed (e.g.
Section 4-10 Program Execution 4-10 Program Execution When program execution is started, the CPU cycles the program from top to bottom, checking all conditions and executing all instructions accordingly as it moves down the bus bar. It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word is used as the operand for an instruction.
SECTION 5 Instruction Set The C200H PC has a large programming instruction set that allows for easy programming of complicated control processes. This section explains each instruction individually and provides the ladder diagram symbol, data areas, and flags used with each. The many instructions provided by the C200H are organized in the following subsections by instruction group.
5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 96 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-1 BCD-TO-BINARY – BIN(23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-2 DOUBLE BCD-TO-DOUBLE BINARY – BINL(58) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-3 BINARY-TO-BCD – BCD(24) . . . . .
Data Areas, Definer Values, and Flags 5-1 Section 5-3 Notation In the remainder of this manual, all instructions will be referred to by their mnemonics. For example, the Output instruction will be called OUT; the AND Load instruction, AND LD. If you’re not sure of the instruction a mnemonic is used for, refer to Appendix B Programming Instructions. If an instruction is assigned a function code, it will be given in parentheses after the mnemonic.
Section 5-3 Data Areas, Definer Values, and Flags will have access to the other area. The border between the IR and SR areas can, however, be crossed for a single operand, i.e., the last bit in the IR area may be specified for an operand that requires more than one word as long as the SR area is also allowed for that operand. The Flags subsection lists flags that are affected by execution of an instruction. These flags include the following SR area flags.
Section 5-4 Differentiated Instructions 5-4 Differentiated Instructions Most instructions are provided in both differentiated and non-differentiated forms. Differentiated instructions are distinguished by an @ in front of the instruction mnemonic. A non-differentiated instruction is executed each time it is cycled as long as its execution condition is ON. A differentiated instruction is executed only once after its execution condition goes from OFF to ON.
Coding Right-hand Instructions 5-5 Section 5-5 Coding Right-hand Instructions Writing mnemonic code for ladder instructions is described in Section 4 Writing and Inputting the Program. Converting the information in the ladder diagram symbol for all other instructions follows the same pattern, as described below, and is not specified for each instruction individually. The first word of any instruction defines the instruction and provides any definers.
Section 5-5 Coding Right-hand Instructions The following diagram and corresponding mnemonic code illustrates the points described above.
Section 5-6 Ladder Diagram Instructions LD or LD NOT, to form ‘logic blocks’ that are combined by the right-hand instruction. An example of this for SFT(10) is shown below.
Section 5-6 Ladder Diagram Instructions B: Bit OR – OR B OR NOT – OR NOT B IR, SR, AR, HR, TC, LR B: Bit IR, SR, AR, HR, TC, LR Limitations There is no limit to the number of any of these instructions, or restrictions in the order in which they must be used, as long as the memory capacity of the PC is not exceeded. Description These six basic instructions correspond to the conditions on a ladder diagram.
Section 5-7 Bit Control Instructions In order to draw ladder diagrams, it is not necessary to use AND LD and OR LD instructions, nor are they necessary when inputting ladder diagrams directly, as is possible from the GPC. They are required, however, to convert the program to and input it in mnemonic form. The procedures for these, limitations for different procedures, and examples are provided in 4-6 Inputting, Modifying, and Checking the Program.
Section 5-7 Bit Control Instructions Flags 5-7-2 There are no flags affected by these instructions. DIFFERENTIATE UP and DOWN – DIFU(13) and DIFD(14) Ladder Symbols Operand Data Areas DIFU(13) B B: Bit IR, AR, HR, LR DIFD(14) B B: Bit IR, AR, HR, LR Limitations Any output bit can generally be used in only one instruction that controls its status. Refer to 3-3 IR Area for details. Description DIFU(13) and DIFD(14) are used to turn the designated bit ON for one cycle only.
Section 5-7 Bit Control Instructions ample of how DIFU(13) can be used to ensure that CMP(20) is executed only once each time the desired execution condition goes ON.
Section 5-7 Bit Control Instructions the set input; R, the reset input. KEEP(11) operates like a latching relay that is set by S and reset by R. When S turns ON, the designated bit will go ON and stay ON until reset, regardless of whether S stays ON or goes OFF. When R turns ON, the designated bit will go OFF and stay OFF until reset, regardless of whether R stays ON or goes OFF. The relationship between execution conditions and KEEP(11) bit status is shown below.
Section 5-8 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Example If a HR bit or an AR bit is used, bit status will be retained even during a power interruption. KEEP(11) can thus be used to program bits that will maintain status after restarting the PC following a power interruption. An example of this that can be used to produce a warning display following a system shutdown for an emergency situation is shown below. Bits 00002, 00003, and 00004 would be turned ON to indicate some type of error.
Section 5-8 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be used several times in a row, with each IL(02) creating an interlocked section through the next ILC(03). ILC(03) cannot be used unless there is at least one IL(02) between it and any previous ILC(03).
Section 5-9 JUMP and JUMP END – JMP(04) and JME(05) The following diagram shows IL(02) being used twice with one ILC(03). Example Address 00000 IL(02) 00001 TIM TIM511 511 #0015 001.
Section 5-10 END – END(01) any instructions in between. The status of timers, counters, bits used in OUT, bits used in OUT NOT, and all other status bits controlled by the instructions between JMP(04) and JMP(05) will not be changed. Each of these jump numbers can be used to define only one jump. Because all of instructions between JMP(04) and JME(05) are skipped, jump numbers 01 through 99 can be used to reduce cycle time.
Timer and Counter Instructions 5-11 NO OPERATION – NOP(00) Description Flags 5-12 Section 5-12 NOP(00) is not generally required in programming and there is no ladder symbol for it. When NOP(00) is found in a program, nothing is executed and the program execution moves to the next instruction. When memory is cleared prior to programming, NOP(00) is written at all addresses. NOP(00) can be input through the 00 function code. There are no flags affected by NOP(00).
Section 5-12 Timer and Counter Instructions 5-12-1 TIMER – TIM Definer Values N: TC number Ladder Symbol # (000 through 511) TIM N SV Operand Data Areas SV: Set value (word, BCD) IR, AR, DM, HR, LR, # Limitations SV is between 000.0 and 999.9. The decimal point is not entered. The SV of the timers can be set in the range #0000 to #9999 (BCD). If the SV for a timer is set to #0000 or #0001, it will operate in the following way.
Section 5-12 Timer and Counter Instructions Flags ER: SV is not in BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) Examples All of the following examples use OUT in diagrams that would generally be used to control output bits in the IR area. There is no reason, however, why these diagrams cannot be modified to control execution of other instructions.
Section 5-12 Timer and Counter Instructions To create delays, the Completion Flags for two TIM are used to determine the execution conditions for setting and reset the bit designated for KEEP(11). The bit whose manipulation is to be delayed is used in KEEP(11). Turning ON and OFF the bit designated for KEEP(11) is thus delayed by the SV for the two TIM. The two SV could naturally be the same if desired. In the following example, 00500 would be turned ON 5.
Section 5-12 Timer and Counter Instructions 01000 TIM 001 01000 00000 01000 TIM 001 #0015 001.5 s Address Instruction 00000 00001 00002 00003 00004 00005 LD AND NOT OR OUT LD TIM 00006 00007 00008 LD AND NOT OUT Operands TIM # 01000 TIM 001 00204 TIM 01000 001 00000 01000 01000 001 0015 01000 001 00204 00000 00204 1.5 s 1.5 s The following one-shot timer may be used to save memory. 00000 Address TIM 001 #0015 00100 001.
Section 5-12 Timer and Counter Instructions A simpler but less flexible method of creating a flicker bit is to AND one of the SR area clock pulse bits with the execution condition that is to be ON when the flicker bit is operating. Although this method does not use TIM, it is included here for comparison. This method is more limited because the ON and OFF times must be the same and they depend on the clock pulse bits available in the SR area.
Section 5-12 Timer and Counter Instructions The SV of the timers can be set in the range #0000 to #9999 (BCD). If the SV for a timer is set to #0000 or #0001, it will operate in the following way. If the SV is set to #0000, when the timer input goes from OFF to ON, the Completion Flag will turn ON. There may be a time delay if TC 000 to TC 003 are used. If the SV is set to #0001, because the timer accuracy is 0 to –0.1 s, the actual time will be a value between 0 and 0.
Section 5-12 Timer and Counter Instructions Execution condition on count pulse (CP) ON Execution condition on reset (R) ON OFF OFF ON Completion Flag OFF SV SV PV 0002 SV – 1 0001 SV – 2 0000 Program execution will continue even if a non-BCD SV is used, but the SV will not be correct. Precautions Flags ER: SV is not in BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-12 Timer and Counter Instructions In the following example, 00000 is used to control when CNT 001 operates. CNT 001, when 00000 is ON, counts down the number of OFF to ON changes in 00001. CNT 001 is reset by its Completion Flag, i.e., it starts counting again as soon as its PV reaches zero. CNT 002 counts the number of times the Completion Flag for CNT 001 goes ON. Bit 00002 serves as a reset for the entire extended counter, resetting both CNT 001 and CNT 002 when it is OFF.
Section 5-12 Timer and Counter Instructions 00000 TIM 001 CNT 002 TIM 001 #0050 TIM 001 005.0 s CP CNT 002 Address Instruction 00000 00001 00002 00003 LD AND NOT AND NOT TIM 00004 00005 00006 LD LD CNT 00007 00008 LD OUT 00001 #0100 R CNT 002 00201 Operands 00000 001 002 001 0050 001 00001 002 0100 002 00201 TIM CNT # TIM # CNT In the following example, CNT 001 counts the number of times the 1-second clock pulse bit (25502) goes from OFF to ON.
Section 5-12 Timer and Counter Instructions The present value (PV) will be incremented by one whenever CNTR(12) is executed with an ON execution condition for II and the last execution condition for II was OFF. The present value (PV) will be decremented by one whenever CNTR(12) is executed with an ON execution condition for DI and the last execution condition for DI was OFF. If OFF to ON changes have occurred in both II and DI since the last execution, the PV will not be changed.
Section 5-13 Data Shifting 5-13 Data Shifting All of the instructions described in this section are used to shift data, but in differing amounts and directions. The first shift instruction, SFT(10), shifts an execution condition into a shift register; the rest of the instructions shift data that is already in memory.
Section 5-13 Data Shifting Example 1: Basic Application The following example uses the 1-second clock pulse bit (25502) so that the execution condition produced by 00005 is shifted into a 3-word register between IR 010 and IR 012 every second.
Section 5-13 Data Shifting used to detect faulty products in the shoot so that the pusher output and HR 0003 of the shift register can be reset as required.
Section 5-13 Data Shifting tion, the status to be put into the register, the shift pulse, and the reset input. The control word is allocated as follows: 15 14 13 12 Not used.
Section 5-13 Data Shifting 5-13-3 ARITHMETIC SHIFT LEFT – ASL(25) Ladder Symbols Description Operand Data Areas ASL(25) @ASL(25) Wd Wd Wd: Shift word IR, AR, DM, HR, LR When the execution condition is OFF, ASL(25) is not executed. When the execution condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
Section 5-13 Data Shifting 5-13-5 ROTATE LEFT – ROL(27) Ladder Symbols Description Precautions Flags 5-13-6 Operand Data Areas ROL(27) @ROL(27) Wd Wd Wd: Rotate word IR, AR, DM, HR, LR When the execution condition is OFF, ROL(27) is not executed. When the execution condition is ON, ROL(27) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd into CY.
Section 5-13 Data Shifting Flags 5-13-7 ER: Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) CY: Receives the data of bit 15. EQ: ON when the content of Wd is zero; otherwise OFF.
Section 5-13 Data Shifting Limitations St and E must be in the same data area, and E must be less than or equal to St. Description When the execution condition is OFF, SRD(75) is not executed. When the execution condition is ON, SRD(75) shifts data between St and E (inclusive) by one digit (four bits) to the right. 0 is written into the leftmost digit of St and the rightmost digit of E is lost. St 3 4 5 2 ...
Section 5-13 Data Shifting Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) 5-13-10 REVERSIBLE WORD SHIFT – RWS(17) Operand Data Areas C: Control word Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # RWS(17) RWS(17) St: Starting word C C IR, AR, DM, HR, LR St St E E E: End word IR, AR, DM, HR, LR Limitations Can be performed with the CPU11-E only.
Section 5-14 Data Movement be set to 0000. The data changes that would occur for the given register and control word contents are also shown.
Section 5-14 Data Movement EQ: 5-14-2 ON when all zeros are transferred to D. MOVE NOT – MVN(22) Ladder Symbols Operand Data Areas S: Source word MVN(22) @MVN(22) S S D D IR, SR, AR, DM, HR, TC, LR, # D: Destination word Description IR, AR, DM, HR, LR When the execution condition is OFF, MVN(22) is not executed. When the execution condition is ON, MVN(22) transfers the inverted content of S (specified word or four-digit hexadecimal constant) to D, i.e.
Section 5-14 Data Movement C Bit 15 Bit 00 S S+1 S+2 S+3 . . . 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 S+15 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 . . . . . . . . . Bit 15 D Flags ER: 0 Bit 00 . . . 0 1 1 1 The column bit designator C is not BCD, or it is specifying a non-existent bit (i.e., bit specification must be between 00 and 15). Indirectly addressed DM word is non-existent.
Section 5-14 Data Movement Bit 15 0 S Bit 00 . . . . . . 0 1 1 1 C Bit 15 Flags . Bit 00 D D+1 D+2 D+3 . . . 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 D+15 0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 . . . . . . ER: . . . The bit designator C is not BCD, or it is specifying a non-existent bit (i.e., bit specification must be between 00 and 15). Indirectly addressed DM word is non-existent.
Section 5-14 Data Movement S St 3 4 5 2 3 4 5 2 St+1 3 4 5 2 St+2 3 4 5 2 E 3 4 5 2 BSET(71) can be used to change timer/counter PV. (This cannot be done with MOV(21) or MVN(22).) BSET(71) can also be used to clear sections of a data area, i.e., the DM area, to prepare for executing other instructions. Flags ER: St and E are not in the same data area or St is greater than E. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-14 Data Movement 5-14-6 BLOCK TRANSFER – XFER(70) Operand Data Areas N: Number of words (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XFER(70) @XFER(70) N N S S D D S: Starting source word IR, SR, AR, DM, HR, TC, LR D: Starting destination word IR, AR, DM, HR, TC, LR Limitations Both S and D may be in the same data area, but their respective block areas must not overlap. S and S+N must be in the same data area, as must D and D+N.
Section 5-14 Data Movement Description When the execution condition is OFF, XCHG(73) is not executed. When the execution condition is ON, XCHG(73) exchanges the content of E1 and E2. E1 E2 If you want to exchange content of blocks whose size is greater than 1 word, use work words as an intermediate buffer to hold one of the blocks using XFER(70) three times. Flags 5-14-8 Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-14 Data Movement Limitations Of must be a BCD. SBs must be in the same data area as SBs+Of. Description When the execution condition is OFF, COLL(81) is not executed. When the execution condition is ON, COLL(81) copies the content of SBs + Of to D, i.e., Of is added to SBs to determine the source word. Flags SBs + Of D 3 4 5 2 3 4 5 2 ER: Of is not BCD, or when added to the SBs, or when added to the SBs, the resulting address lies outside the data area of the SBs.
Section 5-14 Data Movement 5-14-11 MOVE DIGIT – MOVD(83) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MOVD(83) @MOVD(83) S S Di Di D D Di: Digit designator (BCD) IR, AR, DM, HR, TC, LR, # D: Destination word IR, AR, DM, HR, TC, LR Limitations The rightmost three digits of Di must each be between 0 and 3. Description When the execution condition is OFF, MOVD(83) is not executed.
Section 5-15 Data Comparison 5-15 Data Comparison This section describes the instructions used for comparing data. CMP(20) is used to compare the contents of two words; BCMP(68) is used to determine within which of several preset ranges the content of one word lies; and TCMP(85) is used to determine which of several preset values the content of one word equals.
Section 5-15 Data Comparison The following example shows the comparisons made and the results provided for MCMP(19). Here, the comparison is made during each cycle when 00000 is ON.
Section 5-15 Data Comparison Flags ER: Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON if Cp1 equals Cp2. LE: ON if Cp1 is less than Cp2. GR: ON if Cp1 is greater than Cp2. Flag Example 1: Saving CMP(20) Results 00000 Address C1 < C2 C1 = C2 C1 > C2 GR 25505 OFF OFF ON EQ 25506 OFF ON OFF LE 25507 ON OFF OFF The following example shows how to save the comparison result immediately.
Section 5-15 Data Comparison Because all of the comparisons here use to the timer’s PV as reference, the other operand for each CMP(20) must be in 4-digit BCD. 00000 TIM 010 #5000 500.0 s CMP(20) TIM 010 #4000 25507 00200 Output at 100 s. 00200 CMP(20) TIM 010 #3000 25507 00201 Output at 200 s. 00201 CMP(20) TIM 010 #2000 25507 00202 Output at 300 s. 00204 Output at 500 s.
Section 5-15 Data Comparison Limitations Can be performed with the CPU11-E only. Description When the execution condition is OFF, CMPL(60) is not executed. When the execution condition is ON, CMPL(60) joins the 4-digit hexadecimal content of Cp1+1 with that of Cp1, and that of Cp2+1 with that of Cp2 to create two 8-digit hexadecimal numbers, Cp+1,Cp1 and Cp2+1,Cp2. The two 8-digit numbers are then compared and the result is output to the GR, EQ, and LE flags in the SR area.
Section 5-15 Data Comparison 5-15-4 BLOCK COMPARE – BCMP(68) Operand Data Areas CD: Compare data Ladder Symbols IR, SR, DM, HR, TC, LR, # BCMP(68) @BCMP(68) CD CD CB CB R R CB: First comparison block word IR, SR, DM, HR, TC, LR R: Result word IR, AR, DM, HR, TC, LR Limitations Each lower limit word in the comparison block must be less than or equal to the upper limit. Description When the execution condition is OFF, BCMP(68) is not executed.
Section 5-15 Data Comparison The following example shows the comparisons made and the results provided for BCMP(68). Here, the comparison is made during each cycle when 00000 is ON. Example 00000 BCMP(68) Address Instruction 00000 00001 LD BCMP(88) 001 HR 10 Operands 00000 HR 05 HR HR CD 001 001 Lower limits 0210 HR 10 HR 12 HR 14 HR 16 HR 18 HR 20 HR 22 HR 24 HR 26 HR 28 HR 30 HR 32 HR 34 HR 36 HR 38 HR 40 Compare data in IR 001 (which contains 0210) with the given ranges.
Section 5-15 Data Comparison Example The following example shows the comparisons made and the results provided for TCMP(85). Here, the comparison is made during each cycle when 00000 is ON. 00000 TCMP(85) 001 Address Instruction 00000 00001 LD TCMP(85) Operands 00000 HR 10 HR 05 CD: 001 001 Upper limits 0210 Compare the data in IR 001 with the given ranges.
Section 5-16 Data Conversion 5-16 Data Conversion The conversion instructions convert word data that is in one format into another format and output the converted data to specified result word(s). Conversions are available to convert between binary (hexadecimal) and BCD, to 7-segment display data, to ASCII, and between multiplexed and non-multiplexed data. All of these instructions change only the content of the words to which converted data is being moved, i.e.
Section 5-16 Data Conversion Description Flags When the execution condition is OFF, BINL(58) is not executed. When the execution condition is ON, BINL(58) converts an eight-digit number in S and S+1 into 32-bit binary data, and outputs the converted data to R and R+1. BCD S+1 S Binary R+1 R ER: The contents of S and/or S+1 words are not BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) ON when the result is zero.
Section 5-16 Data Conversion 5-16-4 DOUBLE BINARY-TO-DOUBLE BCD – BCDL(59) Ladder Symbols Operand Data Areas S: First source word (binary) BCDL(59) @BCDL(59) S S R R IR, SR, AR, DM, HR, LR R: First result word IR, AR, DM, HR, LR Limitations If the content of S exceeds 05F5E0FF, the converted result would exceed 99999999 and BCDL(59) will not be executed. When the instruction is not executed, the content of R and R+1 remain unchanged.
Section 5-16 Data Conversion For the source data, the seconds is designated in bits 00 through 07 and the minutes is designated in bits 08 through 15 of S. The hours is designated in S+1. The maximum is thus 9,999 hours, 59 minutes, and 59 seconds. The results is output to R and R+1. The maximum obtainable value is 35,999,999 seconds. Flags ER: S and S+1 or R and R+1 are not in the same data area. S and/or S+1 do not contain BCD. Number of seconds and/or minutes exceeds 59.
Section 5-16 Data Conversion For the results, the seconds is placed in bits 00 through 07 and the minutes is placed in bits 08 through 15 of R. The hours is placed in R+1. The maximum will be 9,999 hours, 59 minutes, and 59 seconds. Flags ER: S and S+1 or R and R+1 are not in the same data area. S and/or S+1 do not contain BCD or exceed 36,000,000 seconds. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.
Section 5-16 Data Conversion then one bit will be turned ON in each of consecutive words beginning with R. (See examples, below.) The following is an example of a one-digit decode operation from digit number 1 of S, i.e., here Di would be 0001. Source word C Bit C (i.e., bit number 12) turned ON. First result word 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 The first digit and the number of digits to be converted are designated in Di.
Section 5-16 Data Conversion Flags ER: Undefined digit designator, or R plus number of digits exceeds a data area. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) Example The following program converts three digits of data from DM 0020 to bit positions and turns ON the corresponding bits in three consecutive words starting with HR 10.
Section 5-16 Data Conversion All source words must be in the same data area. Description When the execution condition is OFF, DMPX(77) is not executed. When the execution condition is ON, DMPX(77) determines the position of the highest ON bit in S, encodes it into single-digit hexadecimal value corresponding to the bit number of the highest ON bit number, then transfers the hexadecimal value to the specified digit in R.
Section 5-16 Data Conversion Some example Di values and the word-to-digit conversions that they produce are shown below. Di: 0030 Di: 0011 R R S 0 S 0 S+1 1 S+1 1 2 S+2 2 3 S+3 3 Di: 0013 Di: 0032 R Flags S 0 S R 0 S+1 1 S+1 1 2 S+2 2 3 S+3 3 ER: Undefined digit designator, or S plus number of digits exceeds a data area. Content of a source word is zero. Indirectly addressed DM word is non-existent.
Section 5-16 Data Conversion assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word.
Section 5-16 Data Conversion half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are designated in Di. If multiple digits are designated, they will be placed in order starting from the designated half of D, each requiring two digits. If more digits are designated than remain in S (counting from the designated first digit), further digits will be used starting back at the beginning of S. Digit Designator The digits of Di are set as shown below.
Section 5-16 Data Conversion The table underneath shows the original data and converted code for all hexadecimal digits. Di a D S Bit 00 or bit 08 f 1 a 1 1 b 22 0 1 c 0 23 0 1 d 0 20 0 1 e 21 0 1 f 0 22 0 1 g 1 23 1 0 20 0 21 1 22 1 1 23 1 1 20 1 0 21 0 1 22 1 1 23 1 0 20 0 1 21 0 x100 0 x101 1 x102 1 x103 1: Second digit 0 0: One digit 1 2 0 or 1: bits 00 through 07 or 08 through 15. 3 Not used.
Section 5-16 Data Conversion 5-16-10 ASCII CONVERT – ASC(86) Operand Data Areas S: Source word Ladder Symbols IR, SR, AR, DM, HR, TC, LR ASC(86) @ASC(86) S S Di Di D D Di: Digit designator Limitations IR, AR, DM, HR, TC, LR, # D: First destination word IR, AR, DM, HR, LR Di must be within the values given below All destination words must be in the same data area. Description When the execution condition is OFF, ASC(86) is not executed.
Section 5-17 BCD Calculations Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below.
Section 5-17 BCD Calculations The addition and subtraction instructions include CY in the calculation as well as in the result. Be sure to clear CY if its previous status is not required in the calculation, and to use the result placed in CY, if required, before it is changed by execution of any other instruction.
Section 5-17 BCD Calculations 5-17-4 CLEAR CARRY – CLC(41) Ladder Symbols CLC(41) @CLC(41) When the execution condition is OFF, CLC(41) is not executed.When the execution condition is ON, CLC(41) turns OFF CY (SR 25504). CLEAR CARRY is used to reset (turn OFF) CY (SR 25504) to “0”.
Section 5-17 BCD Calculations last digit is preserved in R+1 so that the entire result can be later handled as eight-digit data.
Section 5-17 BCD Calculations Flags ER: Au and/or Ad is not BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) Example CY: ON when there is a carry in the result. EQ: ON when the result is 0. When 00000 is ON, the following program adds two 12-digit numbers, the first contained in LR 20 through LR 22 and the second in DM 0012. The result is placed in LR 10 through HR 13.
Section 5-17 BCD Calculations Flags ER: Mi and/or Su is not BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) CY: ON when the result is negative, i.e., when Mi is less than Su plus CY. EQ: ON when the result is 0. Caution Be sure to clear the carry flag with CLC(41) before executing SUB(31) if its previous status is not required, and check the status of CY after doing a subtraction with SUB(31).
Section 5-17 BCD Calculations turned OFF for at least one cycle (resetting HR 2100) and then turned back ON. TR 0 00002 CLC(41) @SUB(31) 010 First subtraction DM 0100 HR 20 25504 CLC(41) @SUB(31) #0000 HR 20 HR 21 25504 HR 2100 HR 2100 Turned ON to indicate negative result.
Section 5-17 BCD Calculations Second Subtraction 0000 HR 20 –7577 CY –0 HR 20 2423 CY 1 (0000 + (10000 – 7577)) (negative result) In the above case, the program would turn ON HR 2100 to indicate that the value held in HR 20 is negative.
Section 5-17 BCD Calculations and DM 0001 so that a negative result can be subtracted from 0 (inputting an 8-digit constant is not possible). TR 0 00003 CLC(41) First subtraction @SUBL(55) HR 20 120 DM 0100 25504 @BSET(71) #0000 DM 0000 DM 0001 CLC(41) Second subtraction @SUBL(55) DM 0000 DM 0100 DM 0100 25504 HR 2100 HR 2100 Address 00000 00001 00002 00003 Instruction LD OUT CLC(41) @SUBL(55) Turned ON to indicate negative result.
Section 5-17 BCD Calculations 5-17-9 BCD MULTIPLY – MUL(32) Operand Data Areas Md: Multiplicand (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MUL(32) @MUL(32) Md Md Mr Mr R R Mr: Multiplier (BCD) Description IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, AR, DM, HR LR When the execution condition is OFF, MUL(32) is not executed. When the execution condition is ON, MUL(32) multiplies Md by the content of Mr, and places the result In R and R+1.
Section 5-17 BCD Calculations 5-17-10 DOUBLE BCD MULTIPLY – MULL(56) Operand Data Areas Md: First multiplicand word (BCD) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # MULL(56) @MULL(56) Md Md Mr Mr R R Mr: First multiplier word (BCD) Description R: First result word IR, AR, DM, HR LR When the execution condition is OFF, MULL(56) is not executed.
Section 5-17 BCD Calculations is divided by Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1. Remainder Quotient R+1 R Dr Flags ER: Dd Dd or Dr is not in BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON when the result is 0.
Section 5-17 BCD Calculations divided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, the remainder in R+2 and R+3. Remainder R+3 Dr+1 Flags ER: Quotient R+2 Dr R+1 R Dd+1 Dd Dr and Dr+1 contain 0. Dd, Dd+1, Dr, or Dr+1 is not BCD. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON when the result is 0.
Section 5-17 BCD Calculations The mantissa is expressed as a value less than one, i.e., to seven decimal places. First word 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 1 0 1 0 0 0 0 1 0 Exponent (0 to 7) Sign of exponent 0 0 1 0 0 0 1 Mantissa (leftmost 3 digits) 0: + 1: – Second word 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 Mantissa (leftmost 4 digits) = 0.1111111 x 10–2 Flags ER: Dr and Dr+1 contain 0.
Section 5-17 BCD Calculations 00000 @MOV(21) HR 01 #0000 HR 00 0 0 0 0 HR 00 @MOV(21) 0000 #0000 HR 02 @MOV(21) HR 01 4 0 0 0 #4000 HR 00 0 0 0 0 HR 01 @MOV(21) 4000 #4000 HR 03 DM 0000 3 4 5 2 @MOVD(83) DM 0000 #0021 HR 01 4 3 4 5 HR 01 @MOVD(83) 0 HR 00 0 0 0 DM 0000 3 4 5 2 DM 0000 #0300 HR 00 @MOVD(83) HR 01 4 3 4 5 2 HR 00 0 0 0 HR 01 4 3 4 5 2 HR 00 0 0 0 HR 03 4 0 0 7 9 HR 02 0 0 0 DM 0003 2 4 3 6 9 DM 0002 6 2 0 DM 0001 #0021 HR 03 @MOVD(83) DM 0001 #0300
Section 5-17 BCD Calculations 5-17-14 SQUARE ROOT – ROOT(72) Ladder Symbols Operand Data Areas Sq: First source word (BCD) ROOT(72) @ROOT(72) Sq Sq R R IR, SR, AR, DM, HR, TC, LR R: Result word Description IR, AR, DM, HR, LR, When the execution condition is OFF, ROOT(72) is not executed. When the execution condition is ON, ROOT(72) computes the square root of the eight-digit content of Sq and Sq+1 and places the result in R. The fractional portion is truncated.
Section 5-17 BCD Calculations 00000 @BSET(71) DM 0101 0 0 0 #0000 0 0 DM 0100 0 0 0 DM 0100 DM 0101 0000 0000 @MOV(21) 6 0 010 010 1 7 DM 0101 DM 0101 6 0 1 7 @ROOT(72) 0 DM 0100 0 0 0 DM 0100 60170000= 7756.
Section 5-18 Binary Calculations 5-18 Binary Calculations The binary calculation instructions - ADB(50), SBB(51), MLB(52) and DVB(53) - all perform arithmetic operations on hexadecimal data. The addition and subtraction instructions include CY in the calculation as well as in the result. Be sure to clear CY if its previous status is not required in the calculation, and to use the result placed in CY, if required, before it is changed by the execution of any other instruction.
Section 5-18 Binary Calculations In the case below, A6E2 + 80C5 = 127A7. The result is a 5-digit number, so CY (SR 25504) = 1, and the content of R + 1 becomes #0001. + 0 R+1: HR 11 0 0 1 A Au: IR 010 6 E 2 8 Ad: DM 0100 0 C 5 2 R: HR 10 7 A 7 The following example performs eight-digit addition by using ADB(50) twice. ADB(50) is also used to place the carry into DM 0302 (one word greater than the rest of the answer). The complete answer thus ends up in DM 0300 through DM 0302.
Section 5-18 Binary Calculations In the case below, 4F52A6E2 + EC3B80C5 = 13B8E27A7. The sum of the lower 4-digit addition is a 5-digit number, so CY (SR 25504) = 1, and the sum of the higher 4-digit addition is incremented by 1. Lower 4 digits. + A Au: LR 20 6 E 2 8 Ad: DM 0200 0 C 5 Higher 4 digits.
Section 5-18 Binary Calculations HR 11, and either #0000 or #0001 is placed in HR 12 (0001 indicates a negative answer).
Section 5-18 Binary Calculations #0000 – 6851 –1 (from CY = 1) = 0000 + (10000 – 6851 – 1) = 97AE. The content of HR 12, #0001, indicates a negative result. Lower 4 digits. Higher 4 digits.
Section 5-19 Logic Instructions 5-18-4 BINARY DIVIDE – DVB(53) Operand Data Areas Dd: Dividend word (binary) Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # DVB(53) @DVB(53) Dd Dd Dr Dr R R Dr: Divisor word (binary) Description IR, SR, AR, DM, HR, TC, LR, # R: First result word IR, AR, DM, HR LR When the execution condition is OFF, DVB(53) is not executed.
Section 5-19 Logic Instructions Flags Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) ON when the result is 0. ER: EQ: 5-19-2 LOGICAL AND – ANDW(34) Operand Data Areas Ladder Symbols I1: Input 1 IR, SR, AR, DM, HR, TC, LR, # Description ANDW(34) @ANDW(34) I1 I1 I2 I2 R R I2: Input 2 IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, AR, DM, HR, LR When the execution condition is OFF, ANDW(34) is not executed.
Section 5-19 Logic Instructions 15 Example I1 1 00 0 0 1 1 0 0 1 1 0 0 1 1 0 0 15 I2 0 00 1 0 1 0 1 0 1 0 1 0 1 0 1 0 15 1 R Flags 5-19-4 1 1 00 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 ER: Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) EQ: ON when the result is 0.
Section 5-20 Subroutines and Interrupt Control 5-19-5 EXCLUSIVE NOR – XNRW(37) Operand Data Areas I1: Input 1 Ladder Symbols IR, SR, AR, DM, HR, TC, LR, # XNRW(37) @XNRW(37) I1 I1 I2 I2 R R I2: Input 2 Description IR, SR, AR, DM, HR, TC, LR, # R: Result word IR, AR, DM, HR, LR When the execution condition is OFF, XNRW(37) is not executed. When the execution condition is ON, XNRW(37) exclusively NOR’s the contents of I1 and I2 bit-by-bit and places the result in R.
Section 5-20 Subroutines and Interrupt Control Whereas subroutine calls are controlled from within the main program, subroutines activated by interrupts are triggered when the interrupt signal is received. Also, multiple interrupts from different Interrupt Input Units can occur at the same time. To effectively deal with this, the PC employs a priority scheme for handling interrupts.
Section 5-20 Subroutines and Interrupt Control 5-20-3 SUBROUTINE ENTER – SBS(91) Ladder Symbol SBS(91) N Definer Data Areas N: Subroutine number # (00 to 99) Description A subroutine can be executed by placing SBS(91) in the main program at the point where the subroutine is desired. The subroutine number used in SBS(91) indicates the desired subroutine. When SBS(91) is executed (i.e.
Section 5-20 Subroutines and Interrupt Control Although subroutines 00 through 31 can be called by using SBS(91), they are also activated by interrupt signals from Interrupt Input Units. Subroutine 99, which can also be called using SBS(91), is used for the scheduled interrupt. (Refer to the next subsection for details.) The following diagram illustrates program execution flow for various execution conditions for two SBS(91).
Section 5-20 Subroutines and Interrupt Control Limitations D may be a constant only when CC is 000 or 001. D must be a word address when CC is 002. See below for details. INT(89) is used only to control the scheduled interrupts with the C200H and N must be set to 0004. Caution INT(89) cannot be used during execution of step programs or in C2000H Duplex CPUs. Refer to 5-21 Step Instructions for details on step programs. INT(89) is used to control the scheduled interrupt.
Section 5-20 Subroutines and Interrupt Control Example The following program shows the overall structure and operation of the scheduled interrupt. Here, the scheduled subroutine is started and will be repeated every 20 ms. The control flow logic of the main program is unaffected by execution of the scheduled subroutine, i.e., immediately after the sub routine has finished execution, control returns to the point in the main program where it was suspended.
Section 5-21 Step Instructions 5-21 Step Instructions The step instructions STEP(08) and SNXT(09) are used in conjunction to set up breakpoints between sections in a large program so that the sections can be executed as units and reset upon completion. A section of program will usually be defined to correspond to an actual process in the application. (Refer to the application examples later in this section.) A step is like a normal programming code, except that certain instructions (e.g.
Section 5-21 Step Instructions timers in the step are reset to their SVs. Counters, shift registers, and bits used in KEEP(11) maintain status. Two simple steps are shown below.
Section 5-21 Step Instructions Flags 25407: Step Start Flag; turns ON for one cycle when STEP(08) is executed and can be used to reset counters in steps as shown below if necessary.
Section 5-21 Step Instructions The following diagram demonstrates the flow of processing and the switches that are used for execution control.
Section 5-21 Step Instructions the next step. Each step starts when the switch that indicates the previous step has been completed turns ON. 00001 (SW1) SNXT(09) 12800 Process A started. STEP(08) 12800 Process A 00002 (SW2) SNXT(09) 12801 Process A reset. Process B started. STEP(08) 12801 Process B 00003 (SW3) SNXT(09) 12802 Process B reset. Process C started. STEP(08) 12802 Process C 00004 (SW4) SNXT(09) 12803 Process C reset.
Section 5-21 Step Instructions Example 2: Branching Execution The following process requires that a product is processed in one of two ways, depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used. Various sensors are positioned to signal when processes are to start and end.
Section 5-21 Step Instructions start either process A or process B. Both of the steps for these processes end with a SNXT(09) that starts the step for process C. 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0000 00001 (SW A1) 00002 (SW B2) SNXT(09) HR 0001 STEP(08) HR 0000 Process A started. SNXT(09) HR 0002 Process A reset. Process C started. Process A 00003 (SW A2) STEP(08) HR 0001 Process B 00004 (SW B2) SNXT(09) HR 0002 Process B reset. Process C started.
Section 5-21 Step Instructions The following process requires that two parts of a product pass simultaneously through two processes each before they are joined together in a fifth process. Various sensors are positioned to signal when processes are to start and end. Example 3: Parallel Execution SW1 SW3 Process A SW5 SW7 Process B Process E Process D Process C SW2 SW4 SW6 The following diagram demonstrates the flow of processing and the switches that are used for execution control.
Section 5-21 Step Instructions Process B is thus reset directly and process D is reset indirectly before executing the step for process E. 00001 (SW1 and SW2)) SNXT(09) LR 0000 Process A started. Process C started. SNXT(09) LR 0002 STEP(08) LR 0000 Process A 00002 (SW3) SNXT(09) LR 0001 Process A reset. Process B started. STEP(08) LR 0001 Process B 01101 LR 0003 Used to turn off process D. 00004 (SW5 and SW6) SNXT(09) LR 0004 Process E started.
Section 5-22 Special Instructions Address Instruction 00000 00001 00002 00003 LD SNXT(09) SNXT(09) STEP(08) Operands LR LR LR 00001 0000 0002 0000 LD SNXT(09) STEP(08) Instruction 00102 STEP(08) LR LR Operands LR 0002 LR LR 00003 0003 0003 LR 0004 LR 00005 0005 --- Process C 00200 00201 00202 Process A 00100 00101 00102 Address 00002 0001 0001 LD SNXT(09) STEP(08) Process D 00300 STEP(08) Process B Process E 00100 00101 0003 00101 00101 5-22 LD OUT 01101 LR AND SNXT(09) LR
Section 5-22 Special Instructions FAL(06) produces a non-fatal error and FAL(07) produces a fatal error. When FAL(06) is executed with an ON execution condition, the ALARM/ERROR indicator on the front of the CPU will flash, but PC operation will continue. When FALS(07) is executed with an ON execution condition, the ALARM/ERROR indicator will light and PC operation will stop. The system also generates error codes to the FAL area.
Section 5-22 Special Instructions 5-22-3 MESSAGE DISPLAY – MSG(46) Ladder Symbols Description Operand Data Areas MSG(46) @MSG(46) FM FM FM: First message word IR, AR, DM, HR, LR When executed with an ON execution condition, MSG(46) reads eight words of extended ASCII code from FM to FM+7 and displays the message on the Programming Console, GPC, or FIT. The displayed message can be up to 16 characters long, i.e., each ASCII character code requires eight bits (two digits).
Section 5-22 Special Instructions The following example shows the display that would be produced for the instruction and data given when 00000 was ON. If 00001 goes ON, a message will be cleared.
Section 5-22 Special Instructions Flags ER: S and S+15 are not in the same data area. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) Example 5-22-5 Although the display is longer and there is a choice of output devices, the coding LMSG(47) is the same as that for MSG(46). Refer to Example under the previous section for an example using MSG(46).
Section 5-22 Special Instructions Bit Control If the leftmost 8 bits of P contain A3, SYS(49) is used to set set system operating parameters. To be effective, it must be programmed at program address 00001 with LD AR 1001 at program address 00000. Only bits 00, 06, and 07 are used. If bit 00 is 1, the battery check will be excluded from system error checks when PC power is turned ON. If bit 06 is 1, the Force Status Hold Bit (SR 25212) will be turned ON.
Section 5-22 Special Instructions Limitations Can be performed with the CPU11-E only. For trigonometric functions, x, the content of S, must be in BCD form and satisfy the condition 0000 ≤ x ≤ 0900 (0°≤Θ≤ 90°). Description When the execution condition is OFF, VCAL(69) is not executed. When the execution condition is ON, the operation of VCAL(69) depends on the control word C. If C is #0000 or #0001, VCAL(69) computes sin(x) or cos(x)*.
Section 5-22 Special Instructions Linear Approximation VCAL(69) linear approximation is specified when C is a memory address. Word C is the first word of the continuous block of memory containing the linear approximation data. The content of word C specifies the number of line segments in the approximation, and whether the input and output are in BCD or BIN form. Bits 00 to 07 contain the number of line segments less 1, m–1, as binary data.
Section 5-22 Special Instructions In this case, the input data word, IR 010, contains #0014, and f(0014) = #0726 is output to R, IR 011. Y $1F20 $0F00 (x,y) $0726 $0402 (0,0) $0005 5-22-9 $0014 $001A $05F0 X WATCHDOG TIMER REFRESH– WDT(94) Ladder Symbols WDT(94) T Definer Data Areas @WDT(94) T T: Watchdog timer value # (00 to 63) Description When the execution condition is OFF, WDT(94) is not executed.
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions IORF(97) can be used to refresh I/O words allocated to the CPU or an Expansion I/O Rack only. It cannot be used for other I/O words. Limitations St must be less than or equal to E. Description When the execution condition is OFF, IORF(97) is not executed. When the execution condition is ON, all words between St and E will be refreshed. This will be in addition to the normal I/O refresh performed during the CPU’s cycle.
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions send data to a node on the same Subsystem (i.e., network). Refer to the SYSMAC NET Link System Manual for details. Word Bits 00 to 07 Bits 08 to 15 C Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000hex to 03E8hex) C+1 Network number (0 to 127 in 2-digit Bit 14 ON: Operating level 0 hexadecimal, i.e., 00hex to 7Fhex) OFF: Operating level 1 Bits 08 to 13 and 15: Set to 0.
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) There is no SYSMAC NET Link/SYSMAC LINK Unit.
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions SYSMAC LINK Systems Refer to the SYSMAC LINK System Manual for details. Word Bits 00 to 07 Bits 08 to 15 C Number of words (0 to 256 in 4-digit hexadecimal, i.e., 0000hex to 0100hex) C+1 Response time limit (0.1 and 25.4 seconds in 2-digit hexadecimal without decimal point, i.e., 00hex to FFhex) Note: The response time will be 2 seconds if the limit is set to 0hex. There will be no time limit if the time limit is set to FFhex.
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions If multiple SEND(90)/RECV(98) operations are used, the following flags must be used to ensure that any previous operation has completed before attempting further send/receive SEND(90)/RECV(98) operations SR Flag Functions SEND(90)/RECV(98) Enable Flags (SR 25201, SR 25204) OFF during SEND(90)/RECV(98) execution (including command response processing). Do not start a SEND(90)/RECV(98) operation unless this flag is ON.
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions 00000 SEND(90)/RECV(98) Enable Flag 25204 12802 S KEEP(11) 12801 12800 prevents execution of SEND(90) until RECV(98) (below) has completed. IR 00000 is turned ON to start transmission. 12800 R 12800 @MOV(21) #000A DM 0000 @MOV(21) #0000 DM 0001 @MOV(21) #0003 DM 0002 Data is placed into control data words to specify the 10 words to be transmitted to node 3 in operating level 1 of network 00 (NSB).
Section 5-23 SYSMAC NET Link/SYSMAC LINK Instructions Address Instruction 00000 00001 00002 00003 00004 00005 00006 LD AND AND NOT LD KEEP(11) LD @MOV(21) 00007 00008 00009 Operands 00000 25204 12802 12801 12800 12800 # DM 000A 0000 # DM 0000 0001 # DM 0003 00002 AND NOT LD KEEP(11) LD AND AND NOT XFER(70) 12800 12803 12802 12802 25204 25203 # 00026 00027 LD @MOV(21) @MOV(21) 00028 0010 000 0002 00029 0010 0020 0000 12800 25203 00200 12800 25204 12801 00001 25204 00030 00031 00032 000
SECTION 6 Program Execution Timing The timing of various operations must be considered both when writing and debugging a program. The time required to execute the program and perform other CPU operations is important, as is the timing of each signal coming into and leaving the PC in order to achieve the desired control action at the right time. This section explains the cycle and shows how to calculate the cycle time and I/O response times.
Cycle Time 6-1 Section 6-1 Cycle Time To aid in PC operation, the average, maximum, and minimum cycle times can be displayed on the Programming Console or any other Programming Device and the maximum cycle time and current cycle time values are held in AR 26 and AR 27. Understanding the operations that occur during the cycle and the elements that affect cycle time is, however, essential to effective programming and PC operations.
Section 6-1 Cycle Time 6-1-1 CPU01-E, 03-E Cycle Time Power application Clears IR area and resets all timers Initialization on power-up Checks I/O Unit connections Resets watchdog timer Checks hardware and Program Memory Overseeing processes NO Check OK? YES Sets error flags and turns ON or flashes indicator Link Unit servicing Services Link Units ALARM/ERROR ALARM (Flashing) ERROR (Solid ON) Services Peripheral devices Peripheral device servicing PC cycle time Resets watchdog timer and prog
Section 6-1 Cycle Time formed in cyclic fashion, with each scan forming one cycle. The cycle time is the time that is required for the CPU to complete one of these cycles. This cycle includes basically five types of operation. 1, 2, 3... 1. 2. 3. 4. 5. Overseeing Link Unit servicing Peripheral device servicing Program execution I/O refreshing The cycle time is the total time required for the PC to perform all of the above operations.
Section 6-1 Cycle Time Special I/O Unit Refresh Unit Note Time required C200H-ID501/215 0.8 ms each C200H-OD501/215 C200H-MD501/215 0.8 ms each when set for 32 I/O pts. C200H-CT001-V1/CT002 2.2 ms C200H-NC111/NC112 3.0 ms C200H-NC211 6 ms C200H-AD001 2.3 ms C200H-AD002 2.0 ms C200H-DA001 2.0 ms C200H-TS001/TS101 1.8 ms each C200H-TCjjj (see note 1) 4.0 ms each C200H-ASC02 2.0 ms each normally, 6.0 ms for @ format C200H-IDS01-V1/IDS21 2.5 ms each normally, 6.
Section 6-1 Cycle Time 6-1-2 CPU11-E Cycle Time Power application Clears IR area and resets all timers Initialization on power-up Checks I/O Unit connections Resets watchdog timer Overseeing processes Checks hardware and Program Memory NO Check OK? YES Resets watchdog timer and program address counter Sets error flags and turns ON or flashes indicator Program execution Executes program ALARM/ERROR ERROR (Solid ON) ALARM (Flashing) End of program? PC cycle time NO YES SCAN(18) executed? N
Section 6-1 Cycle Time The first three operations immediately after power application are performed only once each time the PC is turned on. The rest of the operations are performed in cyclic fashion, with each scan forming one cycle. The cycle time is the time that is required for the CPU to complete one of these cycles. This cycle includes basically seven types of operation. 1, 2, 3... 1. 2. 3. 4. 5. 6. 7.
Section 6-2 Calculating Cycle Time Even if the cycle time does not exceed the set value of the watchdog timer, a long cycle time can adversely affect the accuracy of system operations as shown in the following table. Cycle time (ms) 6-2 Possible adverse affects 10 or greater TIMH(15) inaccurate when TC 016 through TC 511 are used. 20 or greater 0.02-second clock pulse not accurately readable. 100 or greater 0.1-second clock pulse not accurately readable and Cycle Timer Error Flag (25309) turns ON.
Section 6-2 Calculating Cycle Time Calculations The equation for the cycle time from above is as follows: Cycle time = overseeing time + Link Unit servicing time + peripheral device servicing time + program execution time + I/O refreshing time The overseeing time is fixed at 2.6 ms. Since there are no Link Units mounted, the Link Unit servicing time is 0.
Section 6-3 Instruction Execution Times The overseeing time is fixed at 2.6 ms. A Link Unit is mounted, so the Link Unit servicing time is 8.0 ms. The Programming Console is mounted to the PC and the total cycle time, T, of operations 1, 2, 4, and 5 is greater than 13 ms, so the peripheral device servicing time is (0.06 x T) ms = (0.06 x 18.5) ms = 1.1 ms. The program execution time is 4.7 ms (0.94 µs/instruction times 5,000 instructions).
Section 6-3 Instruction Execution Times Conditions Instruction CNT Constant for SV ON execution time (µs) OFF execution time (µs) 2.25 R: 2.25 IL: 2.25 JMP: 2.25 R: 160 *DM for SV IL: 2.25 JMP: 2.25 NOP(00) --- 0.75 --- END(01) --- 80 --- IL(02) --- 59 35 ILC(03) --- 44 35 JMP(04) --- 69 35 JME(05) --- 47 35 FAL(06) 01 to 99 --- 236 2.25 FAL(06) 00 --- 182 2.25 FALS(07) --- 4.28 ms 2.25 STEP(08) --- 95 2.25 SNXT(09) --- 34 2.
Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) Constant for SV 311 3.
Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) When decrementing a word 82 2.25 When decrementing *DM 167 STC(40) --- 27 1.5 CLC(41) --- 27 1.5 MSG(46) --- 98 2.25 LMSG(47) Constant for SV 290 3.75 *DM for SV 367 TERM(48) --- 161 3.75 SYS(49) --- 2 3.75 ADB(50) Constant + word b word 144 3.
Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) Comparing constant to word-designated table 674 3.75 Comparing *DM b *DM-designated table 926 Trigonometric functions. 488 Linear approximation with a 256 word table 2.71 ms When transferring 1 word 305 When transferring 1,000 words using *DM 16 ms When setting a constant to 1 word 209 When setting *DM ms to 1,000 words using *DM 4.
Section 6-3 Instruction Execution Times ON execution time (µs) OFF execution time (µs) Word b word 270 3.75 *DM b *DM 454 When reading interrupt mask 265 When masking and clearing interrupt 265 1-word transmit 563 1000-word transmit 752 SBS(91) --- 158 2.25 SBN(92) --- --- --- RET(93) --- 198 1.5 WDT(94) --- 35 2.
Section 6-4 I/O Response Time 6-4 I/O Response Time The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU receives the input signal relative to the input refresh period. The I/O response times for a PC not in a Link System are discussed below. For response times for PCs with Link Systems, refer to the relevant System Manual.
Section 6-4 I/O Response Time Maximum I/O Response Time The PC takes longest to respond when it receives the input signal just after the I/O refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time, except that the I/O refresh time would not need to be added in because the input comes just after it rather than before it.
SECTION 7 Program Monitoring and Execution This section provides the procedures for monitoring and controlling the PC through a Programming Console. If you are using a GPC, a FIT, or a computer running LSS, refer to the Operation Manual for procedures on these. 7-1 7-2 Monitoring Operation and Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1-1 Bit/Digit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring Operation and Modifying Data 7-1 Section 7-1 Monitoring Operation and Modifying Data The simplest form of operation monitoring is to display the address whose operand bit status is to be monitored using the Program Read or one of the search operations. As long as the operation is performed in RUN or MONITOR mode, the status of any bit displayed will be indicated.
Section 7-1 Monitoring Operation and Modifying Data LD and OUT can be used only to designate the first address to be displayed; they cannot be used when an address is already being monitored. Key Sequence Clears leftmost address Cancels monitor operation Examples The following examples show various applications of this monitor operation.
Section 7-1 Monitoring Operation and Modifying Data Bit Monitor 00000 00000 LD 00001 00001 ^ ON 00000 CONT 00001 Word Monitor 00000 00000 CHANNEL 00000 CHANNEL LR cL01 FFFF cL00 0000 240 000 01
Section 7-1 Monitoring Operation and Modifying Data Multiple Address Monitoring 00000 00000 TIM 000 T000 0100 00000 T000 0100 00001 T000 0100 00001 T000 OFF 0100 D000000001 T000 ^OFF 0100 D000000001 T000 10FF^ OFF 0100 T000D000000001 0100 10FF^ OFF D000000001 10FF^ OFF Cancels monitoring of leftmost address 0001 OFF 00000 CONT 00000 CHANNEL 00001 DM 0000 Monitor operation canceled 0000000001 S ONR OFF Indicates Force Reset in operation. Indicates Force Set in operation.
Section 7-1 Monitoring Operation and Modifying Data Bit status will remain ON or OFF only as long as the key is held down; the original status will return as soon as the key is released. If a timer is started, the completion flag for it will be turned ON when SV has been reached. SHIFT and PLAY/SET or SHIFT and REC/RESET can be pressed to maintain the status of the bit after the key is released.
Section 7-1 Monitoring Operation and Modifying Data The following displays show what happens when TIM 000 is set with 00100 OFF (i.e., 00500 is turned ON) and what happens when TIM 000 is reset with 00100 ON (i.e., timer starts operation, turning OFF 00500, which is turned back ON when the timer has finished counting down the SV). (This example is performed in MONITOR mode.) 0010000500 ^ OFF^ OFF Monitoring 00100 and 00500. 0010000500 ~ ON^ OFF Indicates that force set/reset is in progress.
Section 7-1 Monitoring Operation and Modifying Data Example The following example shows the displays that appear when Restore Status is carried out normally. 00000 00000 00000FORCE RELE? 00000FORCE RELE END 7-1-4 Hexadecimal/BCD Data Modification When the Bit/Digit Monitor operation is being performed and a BCD or hexadecimal value is leftmost on the display, CHG can be input to change the value. SR words cannot be changed.
Section 7-1 Monitoring Operation and Modifying Data Example The following example shows the effects of changing the PV of a timer. This example is in MONITOR mode 00000 00000 TIM 000 T000 0122 Timing 00000PRES VAL? T000 0119 ???? PV changed Timing 00000PRES VAL? T000 0100 0200 Timing T000 0199 Timing 7-1-5 Hex/ASCII Display Change This operation converts DM data displays from 4-digit hexadecimal data to ASCII and vice versa. Key Sequence Word currently displayed.
Section 7-1 Monitoring Operation and Modifying Data Example 00000 00000 CH DM 0000 D0000 4412 D0000 AB D0000 4142 7-1-6 3-word Monitor To monitor three consecutive words together, specify the lowest numbered word, press MONTR, and then press EXT to display the data contents of the specified word and the two words that follow it. A CLR entry changes the Three-word Monitor operation to a single-word display.
Section 7-1 Monitoring Operation and Modifying Data Example 00000 00000 CHANNEL DM 0000 D0000 89AB D0002D0001D0000 0123 4567 89AB D0003D0002D0001 ABCD 0123 4567 D0004D0003D0002 EF00 ABCD 0123 D0005D0004D0003 1111 EF00 ABCD D0004D0003D0002 EF00 ABCD 0123 D0002 0123 7-1-7 3-word Data Modification This operation changes the contents of a word during the 3-Word Monitor operation. The blinking square indicates where the data can be changed.
Section 7-1 Monitoring Operation and Modifying Data Example D0002D0001D0000 0123 4567 89AB 3-word Monitor in progress. D0002 3CHCHANG? ~0123 4567 89AB Stops in the middle of monitoring. D0002 3CHCHANG? ~0001 4567 89AB D0002 3CHCHANG? 0001~4567 89AB D0002 3CHCHANG? 0001~2345 89AB D0002D0001D0000 0001 2345 89AB D0002D0001D0000 0001 4567 89AB 7-1-8 Resumes previous monitoring.
Section 7-1 Monitoring Operation and Modifying Data Example 00000 00000 CHANNEL 000 c000 MONTR 0000000000001111 c001 MONTR 0000010101010100 00000 CHANNEL 001 00000 00000 CHANNEL DM 0000 D0000 FFFF D0000 MONTR 1111111111111111 D0000 FFFF 00000 CHANNEL DM 0000 0000S0100R0110SR Indicates Force Reset in effect Indicates Force Set in effect 7-1-9 Binary Data Modification This operation assigns a new 16-digit binary value to an IR, HR, AR, LR, or DM word.
Monitoring Operation and Modifying Data Section 7-1 Key Sequence Word currently displayed in binary.
Section 7-1 Monitoring Operation and Modifying Data Example 00000 00000 CHANNEL 000 00000 CHANNEL 001 c001 MONTR 0000010101010101 c001 CHG? 000010101010101 c001 CHG? 1 00010101010101 c001 CHG? 10 0010101010101 c001 CHG? 100 010101010101 c001 CHG? 100S 10101010101 c001 CHG? 100 010101010101 c001 CHG? 10 S010101010101 c001 CHG? 1 RS010101010101 c001 MONTR 10RS010101010101 IR bit 00115 7-1-10 IR bit 00100 Changing Timer/Counter SV There are two ways to change the SV of a timer or counter.
Section 7-1 Monitoring Operation and Modifying Data This operation can be used to change a SV from designation as a constant to a word address designation and visa verse. Key Sequence Example Inputting New SV and Changing to Word Designation The following examples show inputting a new constant, changing from a constant to an address, and incrementing to a new constant.
Section 7-1 Monitoring Operation and Modifying Data Incrementing and Decrementing 00000 00000 TIM 000 00201SRCH TIM 000 00201 TIM DATA #0123 00201 TIM DATA T000 #0123 #???? 00201DATA ? U/D T000 #0123 #0123 Current SV (during change operation) SV before the change 00201DATA ? T000 #0123 #0122 00201DATA ? T000 #0123 #0123 00201DATA ? T000 #0123 #0124 00201DATA ? T000 #0124 #???? 00201 TIM DATA #0124 Returns to original display with new SV 253
Section 7-2 Program Backup and Restore Operations 7-2 Program Backup and Restore Operations Both Program Memory (UM) and DM area data can be backed-up on a standard, commercially available cassette tape recorder. Any dependable magnetic cassette tape of adequate length will suffice. To save a 8K-word program, the tape must be about 15 minutes long (about 2 min. per K word of data). Always allow for about 5 seconds of blank leader tape before the taped data begins.
Section 7-2 Program Backup and Restore Operations Key Sequence A CLR WRITE EXT 0 [Stop address] [File no.] WRITE Start recording with the tape recorder. [Start address] SHIFT REC RESET After about 5 seconds** (Cancel with the CLR key). **These times take the cassette leader tape into consideration according to the following: a) When recording to tape, the leader tape needs to be allowed to pass before the data transmission to the tape player starts.
Section 7-2 Program Backup and Restore Operations Example 00000 00000MT UM:0 DM:1 00000MT FILE NO.00000000 Selecting Program Memory 00000MT FILE NO.86031400 00000MT START ADDR 00000 00000MT START ADDR 00345 Starting address of data to be recorded 00345MT STOP ADDR 03890 Last address 00345MT STOP ADDR 05789 Stop address specified Start recording Continue within 5 seconds 00345MT RECORD FILE NO.86031400 Blinking Recording in progress 02420MT RECORD FILE NO.
Section 7-2 Program Backup and Restore Operations 3. 4. 5. Specify the start address for the data that is to be restored or compared. Start playing the cassette tape. Within 5 seconds, press SHIFT and PLAY/SET to restore data or VER to compare data. Program restoration or comparison continues until END(01) is reached or until the tape is finished, at which time the program size in Kwords is displayed. At that time the program size in Kwords is displayed.
Section 7-2 Program Backup and Restore Operations Example 00000 00000MT UM:0 DM:1 00000MT FILE NO.00000000 00000MT FILE NO.86031400 00000MT START ADDR 00000 00000MT START ADDR 00345 00345MT PLAY FILE NOâ86031400 Restoring in progress 00420MT PLAY FILE NOâ86031400 END reached Comparison in progress 01420MT VER FILE NOâ86031400 END reached 04801MT PLAY END (01)(05.6KW) Restored up to END 04801MT VER END (01)(05.6KW) Stop comparison using CLR 04801MT DISCONTD END (01)(05.
Section 7-2 Program Backup and Restore Operations the preceding sections for details. An example for each operation is given below. Key Sequence 5 second leader tape** B CLR EXT 1 [File no.] Start tape recorder recording. SHIFT Start tape recorder playback.
Section 7-2 Program Backup and Restore Operations Example: Restoring DM Data 00000 00000MT UM:0 DM:1 D0000MT FILE NO.00000000 Selecting the DM area D0000MT FILE NO.00000012 Start tape playback Within 5 seconds D0000MT PLAY FILE NO.00000012 Restoring in progress D0127MT PLAY FILE NO.00000012 Restoring stopped using CLR key. D0127MT DISCONTD FILE NO.00000012 Restoring stopped at the end. D1999MT END FILE NO.
Section 7-2 Program Backup and Restore Operations Example: Comparing DM Data 00000 00000MT UM:0 DM:1 D0000MT FILE NO.00000000 Selecting the DM area D0000MT FILE NO.00000012 Start tape playback Within 5 seconds D0000MT VER FILE NO.00000012 Blinking Comparison in progress D0127MT VER FILE NO.00000012 Stopped verification using CLR Key D0127MT DISCONTD FILE NO.00000012 Verification stopped at the end. D1999VER OK FILE NO.
SECTION 8 Troubleshooting The C200H provides self-diagnostic functions to identify many types of abnormal system conditions. These functions minimize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation. Program input errors are described in 4-6 Inputting, Modifying, and Checking the Program.
Reading and Clearing Errors and Messages 8-1 Section 8-3 Alarm Indicators The ALARM/ERROR indicator on the front of the CPU provides visual indication of an abnormality in the PC. When the indicator is ON (ERROR), a fatal error (i.e., ones that will stop PC operation) has occurred; when the indicator is flashing (ALARM), a nonfatal error has occurred. This indicator is shown in 2-1 Indicators.
Section 8-4 Error Messages 8-4 Error Messages There are basically three types of errors for which messages are displayed: initialization errors, non-fatal operating errors, and fatal operating errors. Most of these are also indicated by FAL number being transferred to the FAL area of the SR area. The type of error can be quickly determined from the indicators on the CPU, as described below for the three types of errors.
Section 8-4 Error Messages POWER and RUN indicators will be lit and the ALARM/ERROR indicator will be flashing. The RUN output will be ON. Error and message FAL no. FAL(06) has been executed in program. Check the FAL number to determine conditions that would cause execution (set by user). Correct according to cause indicated by FAL number (set by user). F8 Watchdog timer has exceeded 100 ms. Program cycle time is longer than recommended. Reduce cycle time if possible.
Section 8-4 Error Messages other fatal operating errors, the POWER and ALARM/ERROR indicators will be lit. The RUN output will be OFF. Error and message FAL no. Power interruption Power has been interrupted for at least 10 ms. Check power supply voltage and power lines. Try to power-up again. None Watchdog timer has exceeded maximum setting (default setting: 130 ms). Restart system in PROGRAM mode and check program. Reduce cycle time or reset watchdog timer if longer time required.
Section 8-5 Error Flags Other Error Messages 8-5 A number of other error messages are detailed within this manual. Errors in program input and debugging can be examined in Section 4 and errors in cassette tape operation are detailed in Section 7-2. Error Flags The following table lists the flags and other information provided in the SR and AR areas that can be used in troubleshooting. Details are provided in 3-4 SR Area and 3-5 AR Area.
Section 8-5 Error Flags AR Area Address(es) Function 0000 to 0009 Special I/O or PC Link Unit Error Flags 0010 SYSMAC LINK/SYSMAC NET Link Level 1 System Error Flags 0011 SYSMAC LINK/SYSMAC NET Link Level 0 System Error Flags 0012 Rack-mounting Host Link Unit Level 1 Error Flag 0013 Rack-mounting Host Link Unit Level 0 Error Flag 0014 Remote I/O Master Unit 1 Error Flag 0015 Remote I/O Master Unit 0 Error Flag 0200 to 0204 Error Flags for Slave Racks 0 to 4 0300 to 0315 Optical I/O Units
Appendix A Standard Models The C200H is a Rack-type PC that can be configured many different ways. Here is a series of tables listing the Units available for the C200H, along with a brief description of the Unit and its model number.
Appendix A Standard Models C200H I/O Units Name Input Units Specifications AC Input Unit DC Input Unit AC/DC Input Unit Analog Timer Unit 8 pts 100 to 120 VAC C200H-IA121 16 pts 100 to 120 VAC C200H-IA122 8 pts 200 to 240 VAC C200H-IA221 16 pts 200 to 240 VAC C200H-IA222 8 pts No-voltage contact; NPN C200H-ID001 8 pts No-voltage contact; PNP C200H-ID002 8 pts 12 to 24 VDC C200H-ID211 16 pts 24 VDC C200H-ID212 8 pts 12 to 24 VAC/DC C200H-IM211 16 pts 24 VAC/DC C200H-IM212
Appendix A Standard Models C200H Special I/O Units All of the following are classified as Special I/O Units except for the ASCII Unit, which is an Intelligent I/O Unit. Name Highdensity I/O Units DC Input Units Transistor Output Units DC Input/ Transistor Output Units Specifications Model number 32 pts 5 VDC (TTL inputs); with high-speed input function C200H-ID501 32 pts 24 VDC; with high-speed inputs 32 pts 0.
Appendix A Standard Models Name Position Control Units Specifications Model number 1 axis Pulse output; speeds: 1 to 99,990 pps C200H-NC111 1 axis Directly connectable to servomotor driver; compat- C200H-NC112 ible with line driver; speeds: 1 to 250,000 pps 2 axis 1 to 250000. pps. 53 pts per axis C200H-NC211 Cam Positioner Unit Detects angles of rotation by means of a resolver and provides ON C200H-CP114 and OFF outputs at specified angles.
Appendix A Standard Models Optional Products Name Specifications Model number I/O Unit Cover Cover for 10-pin terminal block C200H-COV11 Terminal Block Cover Short protection for 10-pin terminal block (package of 10 cov- C200H-COV02 ers); 8 pts. Short protection for 19-pin terminal block (package of 10 cov- C200H-COV03 ers); 12 pts.
Appendix A Standard Models Optical Units Name Specifications Optical I/O Unit No-voltage Input Unit 100 to 120 VAC power supply l 8 pts. APF/PCF 3G5A2-ID001-PE PCF 3G5A2-ID001-E APF/PCF 3G5A2-IM211-PE PCF 3G5A2-IM211-E APF/PCF 3G5A2-IA121-PE PCF 3G5A2-IA121-E APF/PCF 3G5A2-IA221-PE PCF 3G5A2-IA221-E 2A, 250 VAC/24 VDC APF/PCF 3G5A2-OC221-PE (w/relay socket) 8 pts. PCF 3G5A2-OC221-E 1A, 100 to 120/200 to 240 VAC (w/built-in surge killer) 8 pts.
Appendix A Standard Models Optical Fiber Cable Plastic Optical Fiber Cable (APF) APF stands for “All-Plastic Fiber”. This cable can be used to connect only Units having the suffix “-P” in their model number. The maximum length is 20 m. The 3G5A2-PF002 cable comes without connectors and must be assembled by the user. Product Description Model no. Plastic Optical Fiber Cable Cable only (optical connectors not provided) Order in units of 5 m for cable less than 100 m, or in units of 200 m or 500 m.
Appendix A Standard Models Peripheral Devices Product Programming Console Description Model no.
Appendix A Standard Models SYSMAC LINK Unit/SYSMAC NET Link Unit If you are using any of the Units listed in the table below, they must be mounted to a CPU Rack that uses model C200H-CPU11-E as the CPU. Otherwise, these Units will not operate properly. Name SYSMAC LINK Unit Specifications Model number Must be mounted to leftmost 2 slots on Rack with C200H-CPU11-E. Use optical fiber cable.
Appendix B Programming Instructions This appendix provides tables listing the programming instructions used with C200H PCs. The first table summarizes all instructions and gives page references where more detailed information can be found in the body of the manual. The second table gives the execution times for the instructions for both ON and OFF execution conditions.
Appendix B Programming Instructions Function Code Name Mnemonic Page 20 COMPARE CMP 142 21 MOVE MOV 132 22 MOVE NOT MVN 133 23 BCD-TO-BINARY BIN 149 24 BINARY-TO-BCD BCD 150 25 ARITHMETIC SHIFT LEFT ASL 127 26 ARITHMETIC SHIFT RIGHT ASR 127 27 ROTATE LEFT ROL 128 28 ROTATE RIGHT ROR 128 29 COMPLEMENT COM 184 30 BCD ADD ADD 164 31 BCD SUBTRACT SUB 166 32 BCD MULTIPLY MUL 171 33 BCD DIVIDE DIV 172 34 AND WORD ANDW 185 35 OR WORD ORW 185 36
Appendix B Programming Instructions Function Code Name Mnemonic Page 71 BLOCK SET BSET 135 72 SQUARE ROOT ROOT 177 73 DATA EXCHANGE XCHG 137 74 ONE DIGIT SHIFT LEFT SLD 129 75 ONE DIGIT SHIFT RIGHT SRD 129 76 4-TO-16 DECODER MLPX 153 77 16-TO-4 ENCODER DMPX 155 78 7-SEGMENT DECODER SDEC 158 79 FLOATING POINT DIVIDE FDIV 174 80 SINGLE WORD DISTRIBUTE DIST 138 81 DATA COLLECT COLL 138 82 MOVE BIT MOVB 139 83 MOVE DIGIT MOVD 140 84 REVERSIBLE SHIFT REGI
Appendix B Programming Instructions Instruction Execution Times The following table lists the execution times for all instructions that are available for the C200H. The maximum and minimum execution times and the conditions which cause them are given where relevant. When “word” is referred to in the Conditions column, it implies the content of any word except for indirectly addressed DM words. Indirectly addressed DM words, which create longer execution times when used, are indicated by “*DM”.
Appendix B Programming Instructions Conditions Instruction ON execution time (µs) OFF execution time (µs) SNXT(09) --- 34 2.25 SFT(10) With 1-word shift register 181 R: 191 IL: 30 JMP: 30 R: 1.81 ms IL: 30 JMP: 30 With 250-word shift register 1.44 ms KEEP(11) --- 1.
Appendix B Programming Instructions ON execution time (µs) OFF execution time (µs) When shifting a word 72 2.
Appendix B Programming Instructions ON execution time (µs) OFF execution time (µs) Word ÷ constant b word 476 3.75 *DM ÷ *DM b *DM 704 Word + word b word 243 *DM + *DM b *DM 491 Word – word b word 255 *DM – *DM b *DM 504 Word x word b word 1.14 ms *DM x *DM b *DM 1.39 ms Word ÷ word b word 3.25 ms *DM ÷ *DM b *DM 3.
Appendix B Programming Instructions Conditions Instruction SLD(74) When shifting 1 word ON execution time (µs) OFF execution time (µs) 193 3 When shifting 1,000 DM words using *DM 33 ms SRD(75) When shifting 1 word 193 3 When shifting 1,000 DM words using *DM 33 ms MLPX(76) DMPX(77) SDEC(78) FDIV(79) DIST(80) COLL(81) MOVB (82) MOVD(83) SFTR(84) When decoding word to word 203 When decoding *DM to *DM 568 When encoding a word to a word 225 When encoding *DM to *DM 551 When decodi
Appendix B Programming Instructions Basic Instructions Name Mnemonic Symbol AND AND Function Operand Data Areas Logically ANDs the status of the desig- B: nated bit with the current execution condi- IR SR tion. HR AR LR TC B AND LOAD AND LD Logically ANDs the resultant execution None conditions of the preceding logic blocks. AND NOT AND NOT Logically ANDs the inverse of the desig- B: nated bit with the current execution condi- IR SR tion. HR AR LR TC B COUNTER CNT CP A decrementing counter.
Appendix B Programming Instructions Name Mnemonic Symbol Function Operand Data Areas OR LOAD OR LD Logically ORs the resultant execution con- None ditions of the preceding logic blocks. OR NOT OR NOT Logically ORs the inverse of the desig- B: IR nated bit with the execution condition. SR HR AR LR TC B OUTPUT OUT Turns ON B for an ON execution condition; B: turns OFF B for an OFF execution condi- IR SR tion.
Appendix B Programming Instructions Special Instructions Name Mnemonic Symbol Function NO OPERATION NOP(00) Operand Data Areas Nothing is executed and program opera- None tion moves to the next instruction. None END END(01) Required at the end of each program. In- None structions located after END(01) will not be executed.
Appendix B Programming Instructions Name Mnemonic Symbol Function STEP DEFINE STEP(08) B STEP(08) STEP START SNXT(09) SNXT(09) B SHIFT REGISTER SFT(10) I P R SFT(10) St E When used with a control bit (B), defines the start of a new step and resets the previous step. When used without B, it defines the end of step execution. B: IR HR AR LR Used with a control bit (B) to indicate the end of the step, reset the step, and start the next step which has been defined with the same control bit.
Appendix B Programming Instructions Name Mnemonic Symbol Function WORD SHIFT (@)WSFT(16) WSFT(16) St E REVERSIBLE WORD SHIFT (@)RWS(17) (CPU11-E) RWS(17) C St E CYCLE TIME (@)SCAN(18) (CPU11-E) SCAN(18) Mi ––– ––– MULTI-WORD COMPARE (@)MCMP(19) (CPU11-E) MCMP(19) S1 S2 D COMPARE (@)CMP(20) Operand Data Areas The data in the words from the starting word (St) through to the ending word (E), is shifted left in word units, writing all zeros into the starting word.
Appendix B Programming Instructions Name Mnemonic Symbol Function MOVE (@)MOV(21) MOV(21) S D MOVE NOT (@)MVN(22) MVN(22) S D BCD-TO-BINARY (@)BIN(23) BIN(23) S R BINARY-TO-BCD (@)BCD(24) Operand Data Areas Transfers data from source word, (S) to S: IR destination word (D). SR HR AR LR TC DM # D: IR HR AR LR DM Transfers the inverse of the data in the S: IR source word (S) to destination word (D).
Appendix B Programming Instructions Name Mnemonic Symbol ARITHMETIC SHIFT RIGHT (@)ASR(26) Function Each bit within a single word of data (Wd) Wd: is shifted one bit to the right, with zero writ- IR HR ten to bit 15 and bit 00 moving to CY. AR 15 00 LR 0 Wd CY DM ASR(26) Wd ROTATE LEFT (@)ROL(27) Each bit within a single word of data (Wd) Wd: is moved one bit to the left, with bit 15 mov- IR ing to carry (CY), and CY moving to bit 00.
Appendix B Programming Instructions Name Mnemonic Symbol BCD DIVIDE (@)DIV(33) Function Divides the 4-digit BCD dividend (Dd) by the 4-digit BCD divisor (Dr), and outputs the result to the specified result words. R receives the quotient; R + 1 receives the remainder. R and R + 1 must be in the same data area.
Appendix B Programming Instructions Name Mnemonic Symbol Function DECREMENT (@)DEC(39) Operand Data Areas Decrements the value of a 4-digit BCD Wd: IR word by 1, without affecting carry (CY). HR AR LR DM DEC(39) Wd SET CARRY (@)STC(40) Sets the Carry Flag (i.e., turns CY ON). None STC(40) CLEAR CARRY (@)CLC(41) Clears the Carry Flag (i.e, turns CY OFF). None CLC(41) DISPLAY MESSAGE (@)MSG(46) Displays eight words of ASCII code, starting from FM, on the Programming Console or GPC.
Appendix B Programming Instructions Name Mnemonic Symbol SET SYSTEM (@)SYS(49) (CPU11-E) Function Operand Data Areas Used to either control certain operating parameters, or to execute the system commands that can be executed from the AR area. The contents of the leftmost 8 bits (i.e., bits 08 to 15) of P determine which function SYS(49) will have. If they contain A3, then bit 00 specifies whether the battery will be checked, and bit 07 specifies whether I/O status will be maintained on start up.
Appendix B Programming Instructions Name Mnemonic Symbol BINARY DIVIDE (@)DVB(53) Function Divides the 4-digit hexadecimal dividend (Dd) by the 4-digit divisor (Dr), and outputs result to the designated result words ( R and R + 1). R and R + 1 must be in the same data area.
Appendix B Programming Instructions Name Mnemonic Symbol DOUBLE BCD MULTIPLY (@)MULL(56) Function Multiplies the 8-digit BCD multiplicand and 8-digit BCD multiplier, and outputs the result to the specified result words. All words for any one operand must be in the same data area.
Appendix B Programming Instructions Name Mnemonic Symbol DOUBLE BINARY-TO-DOUBLE BCD (@)BCDL(59) Function Converts the binary value of the two source words (S: starting word) into eight digits of BCD data, and outputs the converted data to the two result words (R: starting result word). Both words for any one operand must be in the same data area.
Appendix B Programming Instructions Name Mnemonic Symbol WORD-TO-COLUMN (@)WTC(64) (CPU11-E) Function Places bit data from the source word (S), consecutively into the same numbered bits of the 16 consecutive destination words (where D is the address of the first destination word). Bit 00 from word S is placed into bit C of word D, bit 01 from word S is placed into bit C of word D+1, etc.
Appendix B Programming Instructions Name Mnemonic Symbol Function BLOCK COMPARE (@)BCMP(68) Operand Data Areas Compares a 1-word binary value (S) with the 16 ranges given in the comparison table (CB is the starting word of the comparison block). If the value falls within any of the ranges, the corresponding bits in the result word (R) will be set. The comparison block must be within one data area.
Appendix B Programming Instructions Name Mnemonic Symbol VALUE CALCULATE (@)VCAL(69) (CPU11-E) Function Operand Data Areas Calculates the cosine, or sine of the given degree value, or determines the y-coordinate of the given x value in a previously established line graph. For the sine and cosine conversions, S is entered in BCD as an angle (in the range 0.0 to 90.0 degrees). When calculating the y-coordinate in a graph, S gives the address of the value of the x-coordinate.
Appendix B Programming Instructions Name Mnemonic Symbol BLOCK TRANSFER (@)XFER(70) Function Moves the content of several consecutive source words (S gives the address of the starting source word) to consecutive destination words (D is the starting destination word). All source words must be in the same data area, as must all destination words. Transfers can be within one data area or between two data areas, but the source and destination words must not overlap.
Appendix B Programming Instructions Name Mnemonic Symbol Function ONE DIGIT SHIFT LEFT (@)SLD(74) Operand Data Areas Shifts all data, between the starting word (St) and ending word (E), one digit (four bits) to the left, writing zero into the rightmost digit of the starting word. St and E must be in the same data area.
Appendix B Programming Instructions Name Mnemonic Symbol 7-SEGMENT DECODER (@)SDEC(78) Function Operand Data Areas Converts hexadecimal values from the source word (S) into 7-segment display data. Results are placed in consecutive half-words, starting at the first destination word (D). Di gives digit and destination details. (The rightmost digit gives the first digit to be converted. The next digit to the left gives the number of digits to be converted minus 1.
Appendix B Programming Instructions Name Mnemonic Symbol DATA COLLECT (@)COLL(81) Function Operand Data Areas Extracts data from the source word and writes it to the destination word (D). The source word is determined by adding the offset (Of) to the address of the source base word (SBs).
Appendix B Programming Instructions Name Mnemonic Symbol REVERSIBLE SHIFT REGISTER (@)SFTR(84) Function Operand Data Areas Shifts bits in the specified word or series of words either left or right. Starting (St) and ending words (E) must be specified. Control word (C) contains shift direction, reset input, and data input. (Bit 12: 0 = shift right, 1 = shift left. Bit 13 is the value shifted into the source data, with the bit at the opposite end being moved to CY.
Appendix B Programming Instructions Name Mnemonic Symbol ASCII CONVERT (@)ASC(86) Function Converts hexadecimal digits from the source word (S) into 8-bit ASCII values, starting at leftmost or rightmost half of the starting destination word (D). The rightmost digit of Di designates the first source digit. The next digit to the left gives the number of digits to be converted.
Appendix B Programming Instructions Name Mnemonic Symbol NETWORK SEND (@)SEND(90) (CPU11-E) Function Operand Data Areas Transfers data from n source words (S is the starting word) to the destination words (D is the first address) in node N of the specified network (in a SYSMAC LINK or NET Link System). The format of the control words varies depending on the type of system. In both types of systems, the first control word (C) gives the number of words to be transferred.
Appendix B Programming Instructions Name Mnemonic Symbol SUBROUTINE START SBN(92) Function Operand Data Areas Marks the start of subroutine N. SBN(92) RETURN RET(93) N Marks the end of a subroutine and returns None control to the main program. RET(93) WATCHDOG TIMER REFRESH (@)WDT(94) N: 00 to 99 WDT(94) T Sets the maximum and minimum limits for T: the watchdog timer (normally 0 to 130 ms).
Appendix B Programming Instructions Name Mnemonic Symbol NETWORK RECEIVE (@)RECV(98) (CPU11-E) Function Operand Data Areas Transfers data from the source words (S is the first word) from node N of the specified network (in a SYSMAC LINK or NET Link System) to the destination words starting at D. The format of the control words varies depending on the type of system. In both types of systems, the first control word (C) gives the number of words to be transferred.
Appendix C Programming Console Operations The table below lists the Programming Console operations, a brief description, and the page on which they appear in the body of this manual. All operations are described briefly, and the key sequence for inputting them given, in the tables which form the second part of this appendix. Name Function Reference page Password Input Prompts the user for the access password. 62 Buzzer ON/OFF Controls whether the buzzer will sound for keystroke inputs.
Appendix C Programming Console Operations System Operations Operation/Description Modes* Password Input Controls access to the PC’s programming functions. To gain access to the system once “PASSWORD” has been displayed, press CLR, MONTR, and then CLR. RMP Buzzer ON/OFF The buzzer can be switched to operate whenever Programming Console keys are pressed (as well as for the normal error indication). BZ is displayed in the upper right corner when the buzzer is operative.
Appendix C Programming Console Operations Operation/Description Modes* I/O Table Read Used to read the I/O Table. The display gives the Unit type, location, I/O word allocation, and word multiplier (where applicable). Rack and unit numbers will vary according to the system in use. The EXT key can be pressed to allow Remote I/O Slave Racks and Optical I/O Units to be selected. If shift is pressed before the arrow key, the Rack and unit numbers need not be specified.
Appendix C Programming Console Operations Programming Operations Operation/Description Modes* Address Designation Displays the specified address. Can be used to start programming from a non-zero address or to access an address for editing. Leading zeros need not be entered. The contents of the address will not be displayed until the down key is pressed. The up and down keys can then be used to scroll through the Program Memory. RPM Program Input Used to enter or edit program instructions.
Appendix C Programming Console Operations Operation/Description Modes* Instruction Insert and Instruction Delete The displayed instruction can be deleted, or another instruction can be inserted before it. Care should be taken to avoid inadvertent deletions as there is no way of recovering the instructions other than to re-enter them. When an instruction is deleted all subsequent instruction addresses are automatically adjusted so that there are no empty addresses, or instructions without addresses.
Appendix C Programming Console Operations Monitoring and Data Changing Operations Operation/Description Modes* Bit/Word Monitor Up to six memory addresses, containing either words or bits, or a combination of the two, can be monitored at once. Only three can be displayed at any one time. If operated in RUN or MONITOR mode, the status of monitored bits will also be displayed.
Appendix C Programming Console Operations Operation/Description Modes* Hex/BCD Data Change Used to edit the leftmost BCD or hexadecimal value displayed during a Bit/Word Monitor operation. If a timer or counter is leftmost on the display, the PV will be the value displayed and affected by this operation. It can only be changed in MONITOR mode and only while the timer or counter is operating. SR words cannot be changed using this operation.
Appendix C Programming Console Operations Operation/Description Modes* 3-word Change This operation changes the value of a word displayed during a 3-word Monitor operation. The blinking cursor indicates the word that will be affected by the operation. The cursor can be moved by using the up and down keys. When the cursor is at the desired location, press CHG. After entering the new data, pressing WRITE causes the original data to be overwritten.
Appendix C Programming Console Operations Cassette Tape Operations Operation/Description Modes* Program Memory Save Copies data from the Program Memory to tape. The file no. specified in the instructions provides an identifying address for the information within the tape. Each file number should be used only once per tape. If only a part of the Program Memory is to be stored, the appropriate start and stop addresses must be entered.
Appendix C Programming Console Operations Operation/Description Modes* Program Memory Compare The procedure to compare Program Memory data stored on a tape with that in the PC’s Program Memory area is the same as that for reading it (see above), except that after starting the tape playback, VER should be pressed instead of SHIFT and PLAY/ SET. P Key sequence A EXT CLR 0 [File no.] WRITE Start tape recorder playback.
Appendix D Error and Arithmetic Flag Operation The following table shows the instructions that affect the ER, CY, GT, LT and EQ flags. In general, ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same. EQ also indicates a result of zero for arithmetic operations. Refer to Section 5 Instruction Set for details.
Appendix D Error and Arithmetic Flag Operation Instructions 25503 (ER) MUL(32) 25504 (CY) 25505 (GR) Unaffected Unaffected 25506 (EQ) 25507 (LE) Unaffected DIV(33) ANDW(34) ORW(35) XORW(36) XNRW(37) INC(38) DEC(39) STC(40) Unaffected ON Unaffected Unaffected Unaffected CLC(41) Unaffected OFF Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected MSG(46) LMSG(47) TERM(48) Unaffected SYS(49) ADB(50) Unaffected
Appendix D Error and Arithmetic Flag Operation Instructions 25503 (ER) XCHG(73) 25504 (CY) Unaffected 25505 (GR) 25506 (EQ) 25507 (LE) Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected SLD(74) SRD(75) MLPX(76) DMPX(77) SDEC(78) FDIV(79) DIST(80) COLL(81) MOVB(82) MOVD(83) SFTR(84) TCMP(85) Unaffected Unaffected Unaffected ASC(86) Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected I
Appendix E Data Areas The data areas in the C200H are summarized below. Prefixes are included with bit and word addresses when inputting them is required to designate the area, i.e., bits/words input without a prefix are considered to be IR or SR bits/words. Area Bits Words Notes IR 00000 to 23515 000 to 235 Words 000 through 029 are allocated to I/O Units on the CPU and Expansion I/O Racks as needed. Words 050 through 231 are allocated to Special I/O Units and Units on Remote I/O Racks as needed.
Appendix E Data Areas Dedicated Bits Most of the bits in the SR and AR area are dedicated for specific purposes. These are summarized in the following tables. Refer to 3-4 SR Area and 3-5 AR Area for details. SR Allocations As a rule, SR area bits can be used only for the purposes for which they are dedicated. The SR area contains flags and control bits used for monitoring PC operation, accessing clock pulses, and signalling errors.
Appendix E Data Areas Word(s) 253 254 255 Bit(s) Function 12 Remote I/O Error Flag 13 Normally ON Flag 14 Normally OFF Flag 15 First cycle 00 1-minute clock pulse bit 01 0.02-second clock pulse bit 02 to 06 Reserved for function expansion. Do not use. 07 Step Flag 08 to 14 Reserved for function expansion. Do not use. 15 Special Unit Error Flag (Special I/O, PC Link, Host Link, Remote I/O Master, SYSMAC NET Link, and SYSMAC LINK) 00 0.1-second clock pulse bit 01 0.
Appendix E Data Areas Word(s) Bit(s) Function 01 14/15 Remote I/O Master Unit 1/Unit 0 Restart Bits 02 00 to 04 Error Flags for Slave Racks 0 to 4 05 to 15 Not used.
Appendix F Word Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments, as well as details of work bits, data storage areas, timers, and counters.
I/O Bits Programmer: Word: Bit Program: Unit: Field device Date: Word: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Word: Bit Unit: Field device Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 334 Unit: Field device Word: Notes Page: Notes Unit: Field device Notes
Work Bits Programmer: Program: Area: Bit Word: Usage Date: Area: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Area: Bit Word: Usage Word: Usage Area: Notes Bit 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 10 10 11 11 12 12 13 13 14 14 15 15 Page: Notes Word: Usage Notes 335
Data Storage Programmer: Word 336 Program: Contents Notes Date: Word Contents Page: Notes
Timers and Counters Programmer: TC address T or C Program: Set value Notes Date: TC address T or C Set value Page: Notes 337
Appendix G Program Coding Sheet The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, allowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands. These will be necessary when inputting programs though a Programming Console or other Peripheral Device.
Program Coding Sheet Programmer: Address 340 Instruction Program: Operand(s) Address Instruction Date: Operand(s) Address Instruction Page: Operand(s)
Appendix H Data Conversion Table Decimal BCD Hex Binary 00 00000000 00 00000000 01 00000001 01 00000001 02 00000010 02 00000010 03 00000011 03 00000011 04 00000100 04 00000100 05 00000101 05 00000101 06 00000110 06 00000110 07 00000111 07 00000111 08 00001000 08 00001000 09 00001001 09 00001001 10 00010000 0A 00001010 11 00010001 0B 00001011 12 00010010 0C 00001100 13 00010011 0D 00001101 14 00010100 0E 00001110 15 00010101 0F 00001111 16
Appendix I Extended ASCII Programming Console and Data Access Console Displays Bits 0 to 3 BIN HEX Bits 4 to 7 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 A B C D E F 0000 0 NUL DLE Space 0 @ P ` p 0 @ P ` p 0001 1 SOH DC1 ! 1 A Q a q ! 1 A Q a q 0010 2 STX DC2 " 2 B R b r " 2 B R b r 0011 3 ETX DC3 # 3 C S c s # 3 C S c s 0100 4 EOT DC4 $ 4 D T d t $ 4 D T d t
Glossary address The location in memory where data is stored. For data areas, an address consists of a two-letter data area designation and a number that designates the word and/or bit location. For the UM area, an address designates the instruction location (UM area). In the FM area, the address designates the block location, etc. allocation The process by which the PC assigns certain bits or words in memory for various functions. This includes pairing I/O bits to I/O points on Units.
Glossary cial purposes, such as holding the status input from external devices, while other bits are available for general use in programming. bit address The location in memory where a bit of data is stored. A bit address must specify (sometimes by default) the data area and word that is being addressed, as well as the number of the bit. bit designator An operand that is used to designate the bit or bits of a word to be used by an instruction.
Glossary Control System All of the hardware and software components used to control other devices. A Control System includes the PC System, the PC programs, and all I/O devices that are used to control or obtain feedback from the controlled system. controlled system The devices that are being controlled by a PC System. control signal A signal sent from the PC to effect the operation of the controlled system.
Glossary default A value automatically set by the PC when the user omits to set a specific value. Many devices will assume such default conditions upon the application of power. definer A number used as an operand for an instruction but that serves to define the instruction itself, rather that the data on which the instruction is to operate. Definers include jump numbers, subroutine numbers, etc. delay In tracing, a value that specifies where tracing is to begin in relationship to the trigger.
Glossary are usually the ON/OFF states of bits, or the logical combination of such states, called execution conditions. exection condition The ON or OFF status under which an instruction is executed. The execution condition is determined by the logical combination of conditions on the same instruction line and up to the instruction currently being executed. execution time The time required for the CPU to execute either an individual instruction or an entire program.
Glossary Graphic Programming Console A programming device with advanced programming and debugging capabilities to facilitate PC operation. A Graphic Programming Console is provided with a large display onto which ladder-diagram programs can be written directly in ladder-diagram symbols for input into the PC without conversion to mnemonic form. hardware error An error originating in the hardware structure (electronic components) of the PC, as opposed to a software error, which originates in software (i.e.
Glossary instruction A direction given in the program that tells the PC of an action to be carried out, and which data is to be used in carrying out the action. Instructions can be used to simply turn a bit ON or OFF, or they can perform much more complex actions, such as converting and/or transferring large blocks of data. instruction block A group of instructions that is logically related in a ladder-diagram program.
Glossary PC controlling the Master and a PC connected to the Remote I/O System through an I/O Link Unit or an I/O Link Rack. I/O Link Unit A Unit used with certain PCs to create an I/O Link in an Optical Remote I/O System. I/O point The place at which an input signal enters the PC System, or at which an output signal leaves the PC System. In physical terms, I/O points correspond to terminals or connector pins on a Unit; in terms of programming, an I/O points correspond to I/O bits in the IR area.
Glossary Link Adapter A Unit used to connect communications lines, either to branch the lines or to convert between different types of cable. There are two types of Link Adapter: Branching Link Adapters and Converting Link Adapters. link A hardware or software connection formed between two Units. “Link” can refer either to a part of the physical connection between two Units (e.g.
Glossary Master Short for Remote I/O Master Unit. memory area Any of the areas in the PC used to hold data or programs. mnemonic code A form of a ladder-diagram program that consists of a sequential list of the instructions without using a ladder diagram. Mnemonic code is required to input a program into a PC when using a Programming Console. MONITOR mode A mode of PC operation in which normal program execution is possible, and which allows modification of data held in memory.
Glossary NOT A logic operation which inverts the status of the operand. For example, AND NOT indicates an AND operation with the opposite of the actual status of the operand bit. NSB An acronym for Network Service Board. NSU An acronym for Network Service Unit. OFF The status of an input or output when a signal is said not to be present. The OFF state is generally represented by a low voltage or by non-conductivity, but can be defined as the opposite of either.
Glossary output bit A bit in the IR area that is allocated to hold the status to be sent to an output device. output device An external device that receives signals from the PC System. output point The point at which an output leaves the PC System. Output points correspond physically to terminals or connector pins. output signal A signal being sent to an external device.
Glossary Printer Interface Unit A Unit used to interface a printer so that ladder diagrams and other data can be printed out. program The list of instructions that tells the PC the sequence of control actions to be carried out. Programmable Controller A computerized device that can accept inputs from external devices and generate outputs to external devices according to a program held in memory. Programmable Controllers are used to automate control of external devices.
Glossary Remote I/O Master Unit The Unit in a Remote I/O System through which signals are sent to all other Remote I/O Units. The Remote I/O Master Unit is mounted either to a CPU Rack or an Expansion I/O Rack connected to the CPU Rack. Remote I/O Master Unit is generally abbreviated to Master. Remote I/O Slave Unit A Unit mounted to a Backplane to form a Slave Rack. Remote I/O Slave Unit is generally abbreviated to Slave.
Glossary set The process of turning a bit or signal ON. set value The value from which a decrementing counter starts counting down or to which an incrementing counter counts up (i.e., the maximum count), or the time from which or for which a timer starts timing. Set value is abbreviated SV. shift register One or more words in which data is shifted a specified number of units to the right or left in bit, digit, or word units.
Glossary system error An error generated by the system, as opposed to one resulting from execution of an instruction designed to generate an error. system error message An error message generated by the system, as opposed to one resulting from execution of an instruction designed to generate a message. TC area A data area that can be used only for timers and counters. Each bit in the TC area serves as the access point for the SV, PV, and Completion flag for the timer or counter defined with that bit.
Glossary watchdog timer A timer within the system that ensures that the cycle time stays within specified limits. When limits are reached, either warnings are given or PC operation is stopped depending on the particular limit that is reached. Wired Slave Rack A Slave Rack connected through a Wired Remote I/O Slave Unit. word A unit of data storage in memory that consists of 16 bits. All data areas consists of words. Some data areas can be accessed only by words; others, by either words or bits.
Index A addresses, in data area, 17 applications, precautions, xv AR area, 32–37 arithmetic flags, 98 arithmetic operations, flags, 31 ASCII, converting data, 161 B backup DM area data, 258 program, 254–256 battery CPU11-E Low Battery Flag, 37 Low Battery Flag, 30 BCD calculations, 162–178 converting, 17 definition, 17 binary calculations, 179 definition, 17 bits controlling, 104 forced set/reset, 241 monitoring, 238–241 buzzer, 63 C counters bits in TC area, 40 changing SV, 251 conditions when reset, 11
Index displays converting between hex and ASCII, 245 I/O Unit designations, 68 Programming Console, English/Japanese switch, 62 DM area, saving, restoring, and comparing, 258–261 E ER. See flag, Instruction Execution Error Network Parameter, 37 Optical Transmitting I/O Error, 33 Step, 31 floating-point decimal, division, 174 Floppy Disk Interface Unit.
Index combining with OR, 49 AND LD, 51, 103 combining with OR LD, 54 use in logic blocks, 52 AND NOT, 48, 102 ANDW(34), 185 ASC(86), 161 ASL(25), 127 ASR(26), 127 BCD(24), 150 BCDL(59), 151 BCMP(68), 146 BCNT(67), 207 BIN(23), 149 BINL(58), 149 BSET(71), 135 CLC(41), 164 CMP(20), 142 CNT, 118 CNTR(12), 121 COLL(81), 138 COM(29), 184 CTW(63), 133 DEC(39), 163 DIFD(14), 89, 105–106 using in interlocks, 109 using in jumps, 111 DIFU(13), 89, 105–106 using in interlocks, 109 using in jumps, 111 DIST(80), 138 DIV
Index J–L jump numbers, 110 jumps, 110–111 ladder diagram branching, 83 IL(02) and ILC(03), 85 using TR bits, 83 controlling bit status using DIFU(13) and DIFD(14), 89, 105–106 using KEEP(11), 106–112 using OUT and OUT NOT, 50 converting to mnemonic code, 46–58 display via GPC, FIT, or LSS, 45 instructions combining, AND LD and OR LD, 54 controlling bit status using KEEP(11), 89 using OUT and OUT NOT, 104 format, 97 notation, 97 structure, 45 using logic blocks, 51 ladder diagram instructions, 102–104 Ladd
Index PROM Writer, 6 servicing, 222 power supply, Power-OFF Counter, 36 precautions, xiii applications, xv general, xiv operating environment, xv safety, xiv present value. See PV Printer Interface Unit.
Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W130-E1-05 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version. Revision code Date 2 July 1990 Revised content Complete update. Information on the CPU11 added, including SYSMAC LINK/SYSMAC NET Link Systems, Error History and Calendar/clock functions, and 14 additional instructions.
Revision History Revision code Date 05 June 2003 370 Revised content Page xiv: Precautions added. Pages 21, 28, and 330: ”Data Retention Control Bit” unified to ”I/O Status Hold Bit.” Pages 28 and 29: Section added on operation without a battery.
