Service Manual

No. 1/0
Pin Name
Function
Row address (AX0-AX6, AX8) is detennined by A0-A8 level at the bank
active command cycle
CLK rising edge. (AX7 is don't care.)
Column address
(A YO-A Y7) is detennined by AO-A 7 level at read or write
command cycle CLK rising edge. And this column address become
bun;t
20,21-24,27-30 I
AO-A8
access start address. A8 define precharge mode command cycle, both banks are
prechareged. But A8=low in when A8=high
in precharge command cycle, only
one bank that
is selected A9 (BS) is precharged. And when A8=high in read or
write command cycle, the precharge cycle start automatically after the last data
in bun;t accessing.
31,32
- GND
Ground
33,37
- NC
Not connected.
CKE detennine next CLK is valid or not. If CKE is high next CLK rising edge
is valid. But if CKE is low, next CLK is invalid. If CLK rising edge is invalid,
34
I CKE
internal clock is not asserted and J.l PD4504161 becomes halt operation.
And when
J.l PD4502161 does not in bun;t mode and CKE is negated,
J.l PD4502161 enter power down mode. During power down mode CKE must
keep low level.
35
I
CLK
CLK
is the master clock input pin. The other inputs signals are referenced at
CLK rising edge.
IC14 VDP2
IC CUSTOM CHIP VDP2 QFP YAMAHA IC CUSTOM CHIP VDP2 QFP HH IC CUSTOM CP VDP2 S QFP YAMAHA
Parts No. : 315-5690 Parts No. : 315-5690-02 Parts No. : 315-5890
•Top View
120
121
160
81
40
80
I
I
41
• Block Diagram
scu
I
Bus control
Scroll picture block
Normal
Rotation
picture
t--<r-
picture
coordinate coordinate
calculation calculation
i
Pattern
Window
name
fo-<
f.-
control
control
Character
I-< f.-
Line picture
control control
VRAM Dot data
control
r-1
control
VRAM
-48-
VDP2
~
"
;1-
-A
'-.r-11
-
HN counter & timing generator r
Video process
Color offset
r----
& shadow
Color
computing
1--
control
Priority
f---.-
control
Expanded
picture circuit
Output
data
control
Color RAM
Color RAM
control
Sprite
control
VDP1
1--
I
r--
f-