Service Manual

IC12/13/15/16
IC UPD4502161G5-A12 TSOP NEC
Parts No.: 315-0910-12
IC HM5221605TT-17 TSOP HITACHI
Parts No.: 315-1017-17
IC LC382161T-17 TSOP SANYO
Parts No. :315-1012-17
• Top View & Pin Layout
•Pin Name
Vss
A0-A9
Address inputs
0015
0014
DQO-DQ5 Data inputs/outputs
Vss
CLK
System clock input
0013
CKE
Clock enable
0012
Vee 7
Vee
cs
Chip select
004
0011
RAS
Row address strobe command
005 0010
1Vss
CAS
Col/ address strobe command
009
WE
W ritre enable
008
Vee
DQML,DQMU
DQ mask enable
NC
OOMU
Vee
Supply voltage
CAS 1 CLK
Vss.GND
Ground
CKE
NC No connection
NC
GNO
AS 1 GNO
A7
A6
AS
A3
A4
Vee
Vss
• Description
No.
1/0
Pin Name
Function
l' 7, 13, 25, 38, 44,
-
vee Power supply of internal circuits.
50
4, 10,26,41,47,50
-
vss Ground pins.
2, 3, 5, 6, 8,
9, 11'
12, 39,
40, 42, 43,
l/0
DQ1-DQ16 l/0 pins are the same as conventional DRAM.
45,46,48,49
DQMU controls upper byte and DQML controls lower byte input/output
buffers.
In read mode, DQMU, DQML control output buffer impedance like
conventional
OE. If DQMU, DQML is high, output buffers become high
14,36
I
DQML,DQMU
impedance. If DQMU, DQML is low, output buffers become low imedance.
If
DQMU, DQML is low, output buffers become low impedance.
And when device in write mode,
DQMU, DQML control word mask. If
DQMU, DQML is high input data is not written to memory cell. If DQMU,
DQML is low input data is written to memory cell.
WE CAS RAS have the same names with conventional DRAM. But these pins
15, 16,
17
I WECASRAS
have different definitions with conventional ones. All of these pins only define
command cycle definition. For detail information see command table.
CS low start the command input cycle. When CS
is high, all input are not
18
I cs
referenced. But even if CS is high, internal operations i.e. bank active or burst
are not changed.
19 I A9
A9 is bank select signal (BS). In command cycle, A9=low select bank A and
A9=high select bank
B.
-47-