32X Hardware Manual Doc.
History Provisional Version 1:(May 11, 1994) Introduction, Section 1 - 3.4, 6.2, 6.3 Total 64 pages Provisional Version 2:(May 23, 1994) Sections 3.5, 4.1 - 4.4, 6.1, additions Total 99 pages not created (chapter 5 Usage Examples) Revision (1): (May 25, 1994) Introduction, Chapters 1 and 2 Terminology Title change (Chapter 2) "32x Features" (Configuration) Coordination of items (2.1, 2.
Introduction This manual applis to the development of game software and explains power up booster "32X" hardware functions for the MEGA Drive. Manual Configuration This manual is composed of the following chapters. Chapter 1 Introduction to the 32x Introduces the main function of the 32X. Chapter 2 Configuration Explains the hardware configuration and purpose of each part. Chapter 3 Functions Mapping Explains the layout on CPU address space of each hardware part.
Terminology RISC (Reduced Instruction Set Computer) This computer architecture improves performance by simplifying instructions specifications and has simplified hardware achieving a high efficiency pipeline (parallel process of instructions within the computer). SH2 (SH7095) At the core of the RISC-type CPU in the Hitachi original microcomputer is a 32-bit divider and cache memory. Cache The cache is comparatively small size high-speed memory placed between the large size low-speed memory and the CPU.
Contents 1. 2. 3. 4. 5. 5 Introduction to 32X ...................................................................................................................................... 7 1.1. Introduction to 32X ............................................................................................................................. 8 Configuration ............................................................................................................................................... 9 1.2.
. 6 1.15. Restrictions .................................................................................................................................. 85 Annexes ..................................................................................................................................................... 88 1.16. Master Boot ROM ........................................................................................................................ 89 1.17. Initial program .......................
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1.1. Introduction to 32X The 32X is a power-up booster installed in the MEGA Drive cartridge slot. This adds a bitmap screen of up to 32,768 simultaneous colors and stero sound source that plays PCM data to the graphics and sound of the existing MEGA Drive. Two 32-bit RISC CPUs are mounted for starting screen graphics processing.
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1.2. 32X Block Diagram 32X is made up of the following parts (see Figure 2.1) - MEGA Drive I/F Component (I/F chipbuilt-in) 32X Cartridge SH2 Component SDRAM (2 Mbit) Frame Buffer (1Mbit x 2) VDP Component Color Palette Component (VDP chip built-in) PWM Component (I/F chip built-in) These hardware resources (excluding the SH2 and SDRAM components) contained by 32X are directly controlled by the MEGA Drive 68000 CPU. The ROM cartridge can be read from both the MEGA Drive and 32X.
1.3. About the 32X Block The role and features of each 32X block shown in section 2.1 is explained below. See chapter 3 for more information. MEGA Drive I/F Component This is an interface connecting the 32X to the MEGA Drive. The 32X hardware resources (graphics, sound, and coomunication with SH2) and cartridge ROM are mapped through the MEGA Drive I/F in the MEGA Drive main CPU (68000) address space.
SDRAM Component The 32X has 2Mbits of SDRAM (synchronous DRAM) as its main memory for the SH2 chips. The SH2 program on the cartridge ROM is loaded in the SDRAM, then executed. The SDRAM arranges 16 bytes and reads to the buffer inside the chip†; after which, in order to synchronize to the SH2 clock and transfer sequentially all data after the second data set can be transferred without any restrictions incurred by the operation within the memory.
Color Palette Component The color palette is a 256 word RAM block. When in the packed pixel mode or run length mode, pixel data in the frame buffer select colors (256 colors from among 32,768 colors) indirectly selected in advance. The color selection format is the same whether selecting per frame buffer in the direct color mode, or per color palette in the run-length mode. One color is 16 bits, of which 15 bits are used, and any color can be selected from 32,768 colors.
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1.4. Mapping The 32x hardware can be controlled from both the main CPU SH2 and MEGA Drive 68000. As stated in the last chapter, the layout of each block in the address space of both CPUs is explained here. MEGA Drive Memory Map In using the 32X, the exclusive initial program provided by SEGA is laid out cartridge ROM of 3FAh or more and jumped by the reset vector.
ROM Access when using the 32X The 68000 vector area (00 0000h - 00 00FFh) is assigned by the custom built-in ROM. Because the ROM contents are 88 0200h, 88 0206h, 88 020Ch, … . After 88 0200h (200h of the cartridge ROM), 6-byte JUMP commands are arranged into a jump table. Only when th RV (ROM to VRAM DMA) bit is 1 is it assigned by the cartridge ROM to 100h - 3F FFFFh. ROM access from the SH2 at this time waits until 68000 rewrites the RV bit to 0.
SH2 Memory Map The 32X has two SH2 chips mounted to a common bus. Consequently, memory maps of the two chips shown in Figure 3.2 are the same. The SH2 has a built-in cache memory for increasing the speed of command and data accessing. Access of identical components of the 32X can be accessed by two cache/ cache through addresses. In cases of the cache address, if is read if data of the address to be is in the cache memory.
Cache Area Access Cache memory is memory used for rapidly supplying commands, operans, and data to the CPU. The 32X accesses the cache after commands and data are loaded in the SDRAM. In 32X, after having loaded command and data into the SDRAM, the cache access is performed. The 32X system register and VDP register, among others, must be cachethrough accessed because values through the VDP or other CPU are replaced and the contents of the cache can no longer be guaranteed.
1.5. Registers 32X registers are classified ad shown below. Meanings of the address and set value of each register are also shown.
VDP register Display mode selection Bitmap Mode register Frame buffer switch Frame buffer cotnrol register Screen shift Screen shift control register Data fill for frame buffer Auto Fill Length register Auto Fill Start Address register Auto Fil Data register 20
System Registers [MEGA Drive side] Using the 32X Adapter Control Register (Access : Byte/Word) Bit 15 14 13 12 11 10 9 MD Side R/W FM A1 5100h - FM: REN: RES: ADEN: 8 7 6 5 4 3 2 Read only - REN 1 0 R/W R/W - - - - - RES ADEN VDP Access Authorization 0: MD (Initial value) 1: SH2 SH2 Reset Enable 0: Disable 1: Enable Resets SH2 0: Reset 1: Cancel reset (initialization by the inital program. Change not allowed.
Interrupt issued for SH2 Interrupt Control Register (Access : Byte/Word) Bit 15 14 13 12 11 10 MD Side A1 5102h - INTS: INTM: 9 8 7 6 5 4 3 2 1 0 R/W R/W - - - - - - - - INTS INTM 3 2 1 0 Slave SH2 interrupt command 0: NO OPERATION (initial value) 1: Interrupt command Master SH2 interrupt command 0: NO OPERATION (initial value) 1: Interrupt command Both are automatically cleared if SH2 does not interrupt clear.
Transfers Data to SH2 DMAC Transfers Data to SH2 DMAC (Access : Byte/Word) Bit 15 14 13 12 11 10 9 MD Side A1 5106h - Ful: RV: 8 7 6 5 4 3 Read only FULL - 2 1 0 R/W R/W R/W - - - - 68S 0 RV DMA FIFO Full 0: Can write 1: Cannot write ROM to VRAM DMA 0: NO OPERATION (initial value) 1: DMA Start Allowed The SH2 side cannot access the ROM when RV = 1 (when doing ROM to VRAM DMA, be sure that RV = 1). Waits until value becomes 0 (RV = 0) before accessing.
68K to SH DREQ Destination Address Register (Acces : Word) Bit MD Side A1 510Ch A1 510Eh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - High Order Low Order 0 Sets the SH2 side (SDRAM) address. The DREQ circuit does not use this data. Thus, when the destination address is known beforehand by SH2, or when SH2 doesnít need to know, no settings are nedded.
Refresh Singal Output to Cartridge SEGA TV Register (Acces: Byte/Word) Bit MD Side A1 511Ah CM: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 - - - - - - - - - 0 R/W - - - - - - CM Cartridge Mode 0: ROM (initial value) 1: DRAM This is a SEGA TV exclusive registe, use of this bit with other application is prohibited.
PWM Sound Source Control PWM Control Register (Access: Byte/Word) Bit MD Side A1 5130h 15 14 13 12 11 10 RMD1 0 1 0 1 8 7 6 5 4 - - - Read only - - - TM3~0: RTP: RMD0 0 0 1 1 9 - 3 2 1 0 R/W R/W R/W R/W TM3 TM2 TM1 TM0 RTP RMD0 RMD1 LMD0 LMD1 PWM timer interrupt interval DREQ 1 occurrence enable (SH2 side only) 0: OFF (initial value) 1: ON OUT OFF R L Setting not allowed LMD0 0 0 1 1 LMD1 0 1 0 1 OUT OFF L R Setting not allowed Both cannot be set to L ch or R ch.
L ch Pulse Width Register (Access : Byte/Word) Bit MD Side A1 5134h 15 14 13 12 11 10 9 8 7 Read only FULL EMPTY 6 5 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 Write only - - The value set by bit 11~0 x Scyc becomes the pulse width.
[SH2 side] Interrupt Control for SH2 Interrupt Mask Register (Access : Byte/Word) Bit SH Side 2000 4000h FM: ADEN: CART: HEN: V: H: CMD: PWM: 15 14 13 12 11 10 9 8 7 6 5 4 - - - Read only R/W FM - - - - - ADEN CART HEN 3 2 1 0 R/W R/W R/W R/W V H CMD PWM VDP Access Authorization 0: MEGA DRIVE (initial value) 1: SH2 Adapter enable bit 0: the 32x use prohibited 1: the 32X use allowed Cartridge insert condition 0: Inserted 1: Not inserted H INT approval within V Blank 0: H INT not a
H Count Register (Access : Byte/Word) Bit SH Side 2000 4004h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - Sets H int occurrence interval. Designates byt the number of lines. 0 = each line (initial value). VRES Interrupt Clear Register (Access : Word) Bit SH Side 2000 4014h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write only Clears VRES interrupt (interrupt caused by pressing the MEGA Drive reset button). If not cleared, interrupt will no longer occur.
PWM Interrupt Clear Register (Access : Word) Bit SH Side 2000 401Ch 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write only Clears PWM interrupt (command interrupt). If not cleared, interrupt will no longer occur.
Points to be aware of concerning interrput Ex. 1. 32X has VRESINT, VINT, HINT, CMDINT and PWMINT, but among these, only CMDINT has points which differ from other INT. Interrupt is enabled by the Interrupt Mask Regsiter (2000 4000h) within the SH2 system register, INT occurs, and when INT is masked by the Interrupt Mask Register within the system register before that INT is received, the following will happen : a. VRES INT, VINT, HINT, PWMINT : INT continues to occur unitl each INT is cleared b.
Activating the 32X Custom Component StandBy Changer Register (Access : Word) Bit SH Side 2000 4002h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write only Use with system (Boot ROM). Access to this register from the application is prohibited.
68k to SH DREQ Length Register (Access : Word) Bit SH Side 2000 4010h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Read only See explanation of MEGA Drive register for more. FIFO Register (Access : Word) Bit SH Side 2000 4012h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 Read only See explanation of MEGA Drive register for more.
PWM Sound Source Control PWM Control Register (Access : Byte/Word) Bit SH Side 2000 4030h 15 14 13 12 11 10 9 8 7 6 5 4 - - - R/W R/W R/W R/W R/W - - - - 3 2 1 0 R/W R/W R/W R/W TM3 TM2 TM1 TM0 RTP RMD0 RMD1 LMD0 LMD1 See explanation of MEGA Drive register for more. TM0~3 set the PWM timer interrupt interval and ROM to PWM transfer cycle. Interrupt occurs by cycle register set value x TM cycle. When TM = 1 the interval is the same as the cycle register.
VDP Registers (Both MEGA Drive and SH2 Common) Display mode Selection Bitmap Mode Register (Access : Byte/Word) 15 14 13 12 11 10 9 8 Read only MD Side A1 5180h SH Side 2000 4100h PAL 7 6 5 - - - - - - - PRI 240 - TV format 0: PAL 1: NTSC Switching is possible only during V Blank PRI: Screen priority (explained later) 0: MEGA Drive has priority (initial value) 1: 32X has priority Switching is always allowed, but is valid from the next line.
Frame Buffer Switching Frame Buffer Control Register (Access : Byte/Word) 15 MD Side A1 518Ah SH Side 2000 410Ah VBLK: HBLK: PEN: FEN: FS: 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - - - - Read only VBLK HBLK PEN 1 0 R/W R/W FEN FS V Blank 0: During display period 1: During V Blank H Blank 0: During display period 1: During H Blank Palette Access Approval 0: Access denied 1: Access approved Frame Buffer Authorization 0: Access approved 1: Access denied Frame Buffer Swap 0: Tr
Screen Shift Screen Shift Control Register (Access : Byte/Word) 15 MD Side A1 5182h SH Side 2000 4102h - SFT: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - SFT 3 2 1 0 R/W Screen 1 dot left shift (explianed later) 0: OFF 1: ON Switching is allowed at any time, but is valid from the next line.
1.6. VDP 32X VDP (referred to as VDP thereafter) controls the color display and has two 1 Mbit frame buffer surfaces for control display screens. Display (to the display screen) is synthesized and composed contextually of a single screen (plane) from thses screens and the existing MEGA Drive screen. MEGA Drive Screen Scroll B Scroll A Priority Window Sprite BG Display Screen Priority 32X Screen DRAM0 DRAM1 Figure 3.
Display Mode Enables output of images that correspond to the NTSC format (Japan, USA) and the PAL format (Western Europe). When the 32X image output is not blank, the MEGA Drive display mode should select a resolution that is equal to the 32X resolution. 32X Non blank 320 x 224 pixels Non-blank 320 x 240 pixels Blank Table 3.
VDP Configuration VDP is mapped, as shown below, from SH2 address 2000 4100h and 2400 0000h. These exist as I/O devices for the CPU. As a resulte, acccessing without the color palette is only a cache-through address.
Switching Frame Buffers By switching the FS bit, the DRAM draw previously handled by the CPU is transferred to the VDP and the contents are displayed. In addition, DRAM that has been displayed is mapeed instead in the address space, allowing the draw. For instance, animation can be displayed repeatedly per each single frame (1/60 sec), and for the period equivalent to a single frame (1/60 sec), write process can continue. Frame buffer can be switched only in VBlank.
15 14 13 12 11 10 Read only SH Side 2000 410Ah VBLK HBLK PEN - - - 9 8 7 6 5 4 3 2 1 0 R/W R/W - - - - - - - - FEN FS = 0 SH (Cache-through) DRAM0 2400 0000h Draw DRAM Display 1Mbit 1Mbit 2402 0000h DRAM1 1Mbit Rewrites FS bit during VBLANK FS = 1 SH (Cache-through) DRAM0 2400 0000h Draw DRAM 1Mbit 1Mbit 2402 0000h DRAM1 Display 1Mbit DRAM0 DRAM1 Figure 3.
Color Palette There is one DRAM0 and DRAM1 common color palette in the 32X, and 0~255 palette code can be specified per each pixel. The figure belows shows the correlation between the color data format, SH2 address, and palette code. Any of R, G, B, each with 5 bits, can be selected from among 32 768 colors. The color data format is 16-bit and the color for each pixel can be directly selected (when in the direct color mode), but data size can be kept down by indirect-selecting using the 8bit palette code.
Over Write Image Allows RAM block that is physically identical to the DRAM area to be accessed from this area. When writing data from this area, data on the frame buffer is not changed and remains in its original state when 00h is written in 1 byte units. Figure 3.
Overview of Display Specifications Display Size 320 pixels x 224 pixels or 320 pixels x 240 pixels only the non-interlace mode Display Colors 32 768 color direct or 256 colors from 32 768 colors (color palette) Frame Buffer 1Mbit DRAM x 2 (Line Table Format) Draw Mode Direct Color Mode (16 bit/1 pixel, 32K color direct) Packed Pixel Mode (8 bits/1 pixel, 256 of 32K colors) Run Length Mode (16 bits/continous same color pixels, 256 of 32K colors) Priority (Combine with To combine MEGA Drive scroll A, B and
Line Table Format There are 256 words in the line table in the frame buffer lead. When writing an address in which pixel data for each line is entered, that liine is displayed. The data format following that address can select the three modes explained on the next page. Mode selection is set by combining VDP register bits M1 and M0. (M1, M0) = (0, 0): = (0, 1): = (1, 0): = (1, 1): (Blank display) Packed pixel mode Direct color mode Run length mode Figure 3.
Priority Select whether or not to use the PRI bit of the VDP register, and whether the 32X is to be displayed in front of or behind the MD screen. Also, each through-bit 1-bit is added to the color data. If the PRI bit is used, the pixel that designated the color is displayed in the side opposite of the MD screen. When the MD color code is 0, and when the 32X designates blank by the VDP register, each becomes transparent, the MD background is displayed. Figure 3.
Direct Color Mode This mode directly expresses data of each line from the pixel in the left corner of the screen by each through bit B, G, R (16-bit). From the size of the frame buffer at 320 words per 1 line, 1 Mbit = 65 536 words = 256 words + 320 x 204 words and only 204 lines can be displayed. The number of lines can be increased by making identical line data to be common. Figure 3.
Packed Pixel Mode This mode indirectly expresses data of each line by individual color palette codes (8-bit) from pixels in the left corner of the screen. Since two pixels are expressed by 1 word, and 1 line contains 160 words, 1 Mbit = 65 536 words = 256 words + 160 x 408 words, it is possible to have 408 lines of display data. Figure 3.
Screen Shift Control Because of word units, address data that can be set in the ne table can change the table only in 2-dot units when in the packed pixel mode. As a result, use the screen shift control bit (SFT) to change the display position by 1-dot units for horizontal scrolling. Figure 3.
Run Length Mode In this mode, pixel data is handled in units as the same colors that continue horizontally, and is represented in palette code (8-bit) and continuing number of pixels = run length data (8-bit). Through-bits are valid in this mode as weel. When the run length exceeds 320 pixels for one line of data, the 320 pixels are displayed from the left, and all pixels thereafter are ignored. Figure 3.
FILL Function Auto Fill uses three registers : the start address, word length, and file data. VDP begins the fill operation when writing to the file data register. The portion that exceeds the page border is filled from the start of the page. Because VDP and SH2 DRAM accesses conflict whil executing Auto Fill, do not access from SH2.
Clock Used by the 32X The master clocks for NTSC and PAL used by the MEGA Drive and 32X are diffferent. The 68000 and SH2 system clocks are shown belows as standards. Mega Drive Master Clock Cycle Mck = 1/fos [sec] NTSC fosc = 53.693175 [MHz] PAL fosc = 53.203424 [MHz] 68000 Clock Cycle Vclk = 7Mck, but Mck is the value above. SH2 Clock Cycle Sclk = Vclk/3, but Vclk is the value above.
HBlank and Display Periods Figure 3.15 HBLANK Period and Display Period A: B: C: D: Blank Period Display Period HBLANK - VBLANK HBLANK - XHDISP 100 dot (860 Mck) 320 dot (2560 Mck) 27 dot (224 Mck) 3 dot (24 Mck) VBlank and Display Periods Figure 3.
VDP Register Latch Timing Figure 3.17 VDP Register Latch Timing A: B: C: H Blank - PEN FEN Width H Blank - latch 3 dot 40 Sclk 76 dot (24 Mck) (VDP side refresh) (668 Mck) The register set within interval C is valid at line n (the nth line), and for interval D is valid at line n+1. Please avoid the type of phenomenon in which the VDP register latch and CPU register access overlap. When the DRAM is being refreshed FEN is 1, but access of the DRAM is possible.
1.7. PWM PWM Sound Sound Source 32X outputs a 2 ch pusle wave as a sound source. The integrated wave form converts the pulse width to wave height. A variety of sounds can be produced by continuously cahnging the pusle width. Figure 3.18 32X Sound Source Figure 3.
Functions of 32X PWM There are five registers within the SYS REG are for controlling PWM of the 32X (see section 3.2). It is possible to access from both the SH2 and the MEGA Drive. Since any register can be accessed in bytes, the MEGA Drive side can switch banks and be accessed from the 68000 or Z80.
Cycle and Pulse Width Settings Both the cycle and pulse width are 12-bit and can be set from 0 to 4095. The cycle register obtains the required sampling rate with the set value –1 as a multiple of the base clock cycle. When the set value = 0 the cycle is at a maximum (4095 times the base clock cycle). When the set value = 1 (0 times the base clock cycle) PWM will no longer operate and should not be set. When 1047 is set in the cycle register, for example, the base clock for NTSC is 23.
1.8. SH2 SH2 is a RISC (Reduced Instruction Set Computer) type processor. As with other RISC type processors, it has the following features due to its high speed instruction implementation. Program (application program) run-time is expressed by the product of the following three elements, C, T and I. Program run-time = C x T x I C : cycle number / command, T: cycle time (clock speed), I: instruction number / task Risc type processor executes instruction at high speed by reducing C and T.
Reduced Cycle Time (Increased Clock Speed) Internal operations can be made faster if the clock speed of the processor is increased, but a gap is created between main memory access times, a wait state is produced in the processor, and the effective cycle number per one instruction increases. In order to fill in this difference, SH2 has a built-in 4Kbyte cache memory. The cache shortens access time by 1 line compared to the main memory.
Master and Slave Two SH2 units are packaged on a common external bus in the 32X. SDRAM and 32X hardware resources are connected to this bus and access the periphery while adjusting (bus arbitration) conflicts of the bus. One side, the Master mode, releases the bus only when bus authorization is requested from the outside with bus authorization under normal conditions.
Cache SH2 contains 4-Kbyte cache memory. Since this memory is accessed per 1 cycle, it is effectively executed by reducing the wait states during access to external chips, such as SDRAM, and minimizing command execution pipeline perturbation. Cache Specifications - 4-Kbyte, command/data mixed type 64 entries x 4-way associative, 16-byte line length (selection of 64 entries x 2 ways + 2-kbyte RAM) Data write is write-through type, LRU repress algorithm able to select command only / data only repress.
Cache Overview In SH2, address bit 3~0 is called an intra-line byte address, and the cache handles address space from the lead (0000 0000h) in line units (1line = 16 bytes). In addition, the address bit 31~29 is called the access space specific address, bit 28~10 is called the tag address and bit 9~4 is called the entry address. 31 28 9 3 Access space specific address Tag address Entry address Intra-line byte address 3 19 6 4 Figure 3.
Cache after implemtenig BOOT ROM The BOOT ROM mounted in the 32X, both master and slave, purges (initializes) and enables the cache immediately after SLEEP from the initial program of the MEGA Drive side has been canceled. At this time, 4-way mode, data replace, and command replace can be selected. Initial data is loaded and settings stay unchanged until the application is implemented.
DMA SH2 contains a 2 channel DMA. If transfer request is set to auto request and is within the SH2 address space, transfer betwwen memories can be performed (at generation inside the DMA). When transfert request is done by an external request (DREQ), DMA transfer can be done by the dual address mode for : - channel 0 from FIFO to SH2-side RAM; - channel 1 PWM sound source pulse width register. DMA transfer can be done by the dual address mode.
Master-Slave Communication When communicating for coordination between the master and slave, it is important to know how to properly receive data and take timings. Built-in SCI (Serial Communication I/F) SH2 has one SCI channel. In the 32X, the master and slave are connected to each other making serial communication possible. If data receive interrupt is used, timing is effective in severe cases. Data is iset in the SDRAM described below and timing can be taken by SCI.
68000-SH2 Communication INTS INTM 8 Word Communication Port SH2 Master MEGA Drive 4 Word FIFO SH2 Slave 4 Word FIFO Figure 3.28 68000 and SH2 Communication Communication Port The 32X has an 8 word register that can read and write from both "communication ports" used in 68000 and SH2 communication.
DMA SH2 has a 2 channel DMA built-in to it. When the 32X uses channel 0 from among the two channels, data can be transferred from the MEGA Drive side to the SH2 side. The 32X has a DREQ circuit for issuing transfer requests to channel 0 and a FIFO for continuously transferring data. FIFO can be directly written to by the 68000.
Interrupt There are five ways an interrupt can be created : - pressing the MEGA Drive reset button - during vertical feedback - during horizontal feedback - interrupt control register write from MEGA Drive - PWM cycle timer Each interrupt is cleared when written to an interrupt clear register by a different factor. Interrupt continues indefinitely until cleared. Mask / enable is allowed separately by setting the interrupt mask register V, H, CMD, and PWM bits except fro the reset button.
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1.9. 32X Block Access by SH2 Blocks that Can Be Directly Accessed Access from SH2, 68000, and Z80 to all 32X buffer registers corresponds to the list below (the V mark means access from Z80 is possible).
Cache-through Access System and VDP registers must be accessed by cache-through. Although system design also allows access by cache, because there is no guarantee that data of an external device or register which could be re-written by other processors would agree with cache data, purge becomes necessary each time. Therefore, cache can not be used.
1.10. 32X Block Access by 68000 Blocks that can be directly accessed After the power is turned on, address space of 68000 is mapped the same as the MEGA Drive unit. If the 32X initial program provided by SEGA is installed following the POWER ON reset vector address, 32X is mapped at the time the execution is transferred to the application program, and is initialized in an access-enabled status. See Table 4.1 "32X Buffer Register List" in section 4.1 for individual buffer registers.
1.11. 32X Block Access by Z80 Blocks that can be directly accessed Z80 is laoded as the MEGA Drive sound CPU. Event when 32X is mapping in the 68000 address space, 68000 memory area can access each 8000h by switching banks similar to when using the Mega Drive unit. See Table 4.1 "32X Buffer Register List" in section 4.1 for individual buffer registers. Competition with other CPUs Access competition to the 32X block of 68000 and SH2 applies to both Z80 and SH2. See section 4.2 for more information.
1.12. Access Timing of each CPU to 32X Block The timing sequence when the CPU accesses the peripheral is called a bus cycle, and takes a minimum of 4 Clock with 68000 and 2 Clock with SH2*. In addition, wait time is created on the CPU side due to the difference of the peripheral and operating speeds. 1 Wait means that the minimum bus cycle + 1 Clock is necessary in the access.
VDP Register SH2 (Read/Write): 68K (Read): 68K (Write): 5 wait (const) 2 wait (const) 0 wait (const) System Register SH2 (Read/Write): 68K (Read/Write): 1 wait (const) 0 wait (const) Boot ROM SH2 (Read): 1 wait (const) SDRAM Access Time The 32X SDRAM is specialized for the "replace" in the case of the SH2 cache miss, and read transfers in the 8 word busrts mode* while write transfers in the 1 word single mode.
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1.13. Boot ROM The Boot ROM is an SH2 execution object that is loaded in 32X as ROM, and is different in content with respect to the master CPU and slave CPU. SH2 itseld sleeps until activated by the Mega Drive side initial program. After the Boot ROM is reactivated, security (see 6.3 Security) is executed by the master CPU; and if OK, the Initial program is executed after the initial data (application program) is loaded from the cartridge to SDRAM.
Mega Drive and SH2 Synchronization The Boot ROM flow chart is shown in Figure 5.2. The "comm 0, 4, 8" reference in the figure below refers to communication ports on the 32X. Immediately before an application starts, SH2 master writes "M_OK" (ASCII code 4 bytes) and SH2 slave writes "S_OK" to the communication port. The Mega Drive side executes the initial program (See 5.2 Security) at this time.
Boot (Master) General Purpose Register Initialization Custom Clear Bus State Cache ON Controller Initialization sleep doesn' exist Cartridge exists N comm0 = "M_OK" Y comm0 = "_CD_" Y N comm0 = "M_OK" N Y "M_OK" comm0 Application Start Figure 5.
1.14. Security Initial Program The Initial program performs hardware security and everything required upon resetting in order to equalize all hardware conditions when the Mega Drive and 32X are powered on. In the application program for 32X, the initial program (ICD_MARS.PRG) that replaces the one used by the current Mega Drive must be included. This program is executed immediately after the power is turned on or reset by the Mega Drive side.
Included in the Initial Program A list of the Mega Drive side sample program is shown in Figure 5.4 below. The initial program (ICD_MARS.PRG) appears in italics. **************************************************************************** * MARS Sample Program * Mega Drive Main Routine * Copyright SEGA ENTREPRISES, LTD 1994 *____________________________________________________ * CS Hardware R&D Dept.
1.15. Restrictions 1. When performing SH2 auto request DMA, both master interrupt and slave interrupt must be masked. If DMA is performed by both master and slave at the same time, one side of DMA will perofrm very slow until the other side of DMA is finished. 2. Since starting the interrupt process may take longer while executing auto request, VDP cannot be accessed within H interrupt whild DMA is occurring. When PWM is used, data write may not happen in time.
Please make the following setting in response to use when transferring with DMAC of SH2. 1. Transfer from DREQ FIFO to memory (channel 0 is used by external request).
Restrictions Concerning SH2 Interrupt The 32X SH2 has five types of interrupt. Level 14 VRES interrupt Level 12 V interrupt Level 10 H interrupt Level 8 Command interrupt Level 6 PWM interrupt The following restrictions occur when using two or more of the following interrupts along with interrupts through the SH2 internal peripheral module at the same time. 1. There should always be 1 or more interrupt masks. Don't use interrupts of level 15, level 13, level11, level 9, level 7 and level 1. 2.
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1.16. Master Boot ROM org $0 dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.
GPRInit: 0x00000144: 0x00000146: 0x00000148: 0x0000014A: 0x0000014C: 0x0000014E: 0x00000150: 0x00000152: 0x00000154: 0x00000156: 0x00000158: 0x0000015A: 0x0000015C: 0x0000015E: 0x00000160: 0xE000 0xE100 0xE200 0xE300 0xE400 0xE500 0xE600 0xE700 0xE800 0xE900 0xEA00 0xEB00 0xEC00 0xED00 0xEE00 BusStateCtrlInit: 0x00000162: 0xD86F 0x00000164: 0xD96F Register 1 0x00000166: 0x6086 0x00000168: 0x1900 0x0000016A: 0x6086 0x0000016C: 0x1901 0x0000016E: 0x6086 0x00000170: 0x1902 0x00000172: 0x6086 0x00000174: 0x19
Register 0x000001B6: 0x000001B8: 0x000001BA: Register 0x000001BC: 0x000001BE: 0xE000 0x2800 0xD95B mov mov.b mov.l #0x00, r0 r0, @r8 @(0x170, pc), r9 0xE011 0x2900 mov mov.b #0x11, r0 r0, @r9 SDRAMInit: 0x000001C0: 0x000001C2: 0x000001C4: 0x000001C6: 0x000001C8: 0x000001CA: 0x000001CC: 0x000001CE: 0x000001D0: 0x000001D2: 0x000001D4: 0x000001D6: 0x000001D8: 0xD860 0xD95F 0xE000 0x2805 0x7001 0x2805 0x7001 0x2805 0x7001 0x2805 0x7001 0x3980 0x8BF5 mov.l mov.l mov mov.w add mov.w add mov.w add mov.
0x00000228: 0xDB06 InitialProgramCheck: 0x0000022A: 0x67C5 0x0000022C: 0x607D 0x0000022E: 0x66D5 0x00000230: 0x616D 0x00000232: 0x3100 0x00000234: 0x8B08 0x00000236: 0x3BC0 0x00000238: 0x8BF7 0x0000023A: 0xA00D 0x0000023C: 0x0009 0x0000023E: 0x0000 org dc.l dc.l mov.w @r12+, r7 extu.w r7, r0 mov.w @r13+, r6 extu.w r6, r1 cmp/eq r0, r1 bf 0x00000248 cmp/eq r12, r11 bf 0x0000022A bra 0x00000258 nop unrecognized mov.l mov.l mov mov.
0x000002A2: 0x8BF9 bf 0x000002A4: 0x000002A6: 0x000002A8: 0x000002AA: 0x000002AC: 0x000002AE: 0x000002B0: 0x000002B2: mov.l @(0x008, r13), r0 ; r0 = Master SH2 VBR from cartridge ldc r0, vbr mov.l @r13, r8 ; r8 = Master SH2 Start Address from cartridge mov.l @(0x02C, pc), r0 ; Put M_OK on CommPort($20) mov.l r0, @(0x020, gbr) jmp @r8 nop unrecognized org dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.
dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l dc.l $0001FFE0 $26000000 $26040000 $A55A0001 $A55A00A8 $A55A0055 $A55A0AB8 $A55A0008 $A55A0000 $A55A0059 $FFFF8446 $5F43445F ; _CD_ org $36C incbin "ip.bin" 0x0000076C: 0xFFFF ... 0x000007FE: 0xFFFF unrecognized unrecognized where ip.bin is move.l #-64,a4 move.l #0,$a15128 and the initial program below.
1.17. Initial program * DIAGNSTC\SOURCE\MD\SOURCE ***************************************************************** * MARS Initial & Security ( Cartridge Mode Only ) * * Copyright SEGA ENTERPRISES,LTD. 1994 * * SEGA ENTERPRISES,LTD. * CS Hardware R&D Dept. * T.Okawa * *---------------------------------------------------------------* * Version 0.5 3/31/94 Version 0.0 Board * Version 1.0 4/12/94 Version 1.0 Board * Version 1.1 4/19/94 Custom IC * Version 1.1a 5/12/94 Custom IC Bug Fix * Version 1.
* * Mega Drive / Genesis Initialize * MARS System Register Initialize * MARS VDP Register Initialize * MARS Frame Buffer Clear * SH2 SDRAM Clear & Program Loading * Check TV Mode * Check SUM Compare * * * * OUT cc/cs "MARS ID" and "Self Check" Complete / Error * * d0.w Error status * bit 0 MARS ID Error * bit 1 TV Mode Error * bit 2 Not used * bit 3 Not used * bit 4 Not used * bit 5 Check Sum Error * bit 6 Security Error * bit 7 SDRAM Self Check Error * | * bit 15 0: Cold Start / 1: Hot Start * * d1.
beq.b cold_start btst.b #0,$5101(a5) bne Hot_Start * power on (cold_start) cold_start: * ---- Security move.b 1(a5),d0 andi.b #$000f,d0 beq.b japan move.l $55a,$4000(a5) japan: moveq #0,d1 move.l d1,a6 move.l a6,usp lea bsr bsr vreg_dt,a0 VdpRegInit VramClear lea z80_prg,a3 lea $a00000,a1 lea $c00011,a2 move.w #$100,d7 moveq #0,d0 * Z80 self_initial z80_clr: move.w d7,$1100(a5) move.w d7,$1200(a5) z801: btst d0,$1100(a5) bne.b z801 moveq #37,d2 z802: move.
z80_prg: dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b dc.b psg_dat: dc.
VramClear: movem.l d0/d7/a0/a1,-(a7) * dc.l $48e781c0 lea lea move.w move.w move.w move.w move.w move.w move.w move.l move.w chk_vdp: move.w btst bne.b fill_data,a0 $c00004,a1 (a0)+,(a1) (a0)+,(a1) (a0)+,(a1) (a0)+,(a1) (a0)+,(a1) (a0)+,(a1) (a0)+,(a1) (a0)+,(a1) d1,-4(a1) ;dma fill(VDP_VRAM CLEAR) ;fill data set $0 (a1),d0 #1,d0 chk_vdp ; DMA end/H move.w (a0)+,(a1) move.w (a0)+,(a1) moveq #0,d0 move.l #$c0000000,(a1) moveq #$80/2/4-1,d7 cclr: vsclr: move.w move.w move.w move.
move.w #$ff,$4(a1) ; Fill Length Reg. move.w d1,$6(a1) move.w d0,$8(a1) nop ; Fill Start Address Reg. ; Fill Data Reg. btst.b bne.b add.w dbra ; FEN = 0 ? fill0: fen0: * #1,$b(a1) fen0 #$100,d1 d7,fill0 ; Address = +200H movem.l (a7)+,d0/d1/d7/a1 dc.l $4cdf0283 rts *----------------------------------------------* Palette RAM Clear *----------------------------------------------PaletteClear: movem.l d0/d7/a0,-(a7) * dc.l $48e78180 lea $a15200,a0 fm2: bclr.b #7,-$100(a0) bne.
* ---- Communication Reg. Clear moveq #0,d0 move.l d0,$20(a1) ; clear "M_OK" move.l d0,$24(a1) ; clear "S_OK" fm3: move.b #3,$5101(a5) move.l $880000,a7 ; SH2 start ; set stack pointer bclr.b bne.b moveq move.w move.w move.w move.l move.l move.w move.w move.w move.w ; MD access #7,(a1) fm3 #0,d0 d0,2(a1) d0,4(a1) d0,6(a1) d0,8(a1) d0,$c(a1) d0,$10(a1) d0,$30(a1) d0,$32(a1) d0,$38(a1) move.w d0,$80(a1) move.w d0,$82(a1) ; ; ; ; ; ; ; ; ; Interrupt Reg. Bank Reg. DREQ Control Reg.
bne tvmodeok: * ---- MarsError CheckSum Compare moveq #$20,d0 lea $880000,a0 move.w $18e(a0),d6 tst.w d6 beq cksumend ; MARS Bank Image Address ; CheckSum Data ; if CheckSum = 0 then No check cksum: move.w $28(a1),d2 cmp.w #0,d2 beq.b cksum cmp.w bne.b cksumend: d6,d2 MarsError ; CheckSum Compare complete: * ---- Communication Reg. Clear moveq #0,d0 move.l d0,$28(a1) ; 8 move.l d0,$2c(a1) ; 12 move.w movea.l movem.l * dc.l move bra.b Hot_Start: lea move.
