Data Sheet

12 | P a g e Espressif Systems Oct 12, 2013
ESP8266 802.11bgn Smart Device
8 CPU, Memory and Interfaces
8.1 CPU
This chip embeds an ultra low power Micro 32-bit CPU, with 16-bit thumb mode. This CPU can
be interfaced using:
 code RAM/ROM interface (iBus) that goes to the memory controller, that can also be
used to access external flash memory,
 data RAM interface (dBus), that also goes to the memory controller
 AHB interface, for register access, and
 JTAG interface for debugging
8.2 Memory Controller
The memory controller contains ROM, and SRAM. It is accessed by the CPU using the iBus,
dBus and AHB interface. Any of these interfaces can request access to the ROM or RAM
modules, and the memory controller arbiters serve these 3 interfaces on a first-come-first-serve
basis.
8.3 AHB and AHB Blocks
The AHB blocks performs the function of an arbiter, controls the AHB interfaces from the MAC,
SDIO (host) and CPU. Depending on the address, the AHB data requests can go into one of the
two slaves:
 APB block, or
 flash controller (usually for standalone applications).
Data requests to the memory controller are usually high speed requests, and requests to the APB
block are usually register access.