Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-C3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 System Clocks
- 3.3 Analog Peripherals
- 3.4 Digital Peripherals
- 3.4.1 General Purpose Input / Output Interface (GPIO)
- 3.4.2 Serial Peripheral Interface (SPI)
- 3.4.3 Universal Asynchronous Receiver Transmitter (UART)
- 3.4.4 I2C Interface
- 3.4.5 I2S Interface
- 3.4.6 Remote Control Peripheral
- 3.4.7 LED PWM Controller
- 3.4.8 General DMA Controller
- 3.4.9 USB Serial/JTAG Controller
- 3.4.10 TWAI® Controller
- 3.5 Radio and Wi-Fi
- 3.6 Bluetooth LE
- 3.7 Low Power Management
- 3.8 Timers
- 3.9 Cryptographic Hardware Accelerators
- 3.10 Physical Security Features
- 3.11 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
4 Electrical Characteristics
Note:
In real-life applications, when VDD_SPI works in 3.3 V output mode, VDD3P3_CPU may be affected by R
SP I
. For
example, when VDD3P3_CPU is used to drive a 3.3 V flash, it should comply with the following specifications:
VDD3P3_CPU > VDD_flash_min + I_flash_max*R
SP I
Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the maximum current.
For more information, please refer to section 2.3 Power Scheme.
4.4 DC Characteristics (3.3 V, 25 °C)
Table 14: DC Characteristics (3.3 V, 25 °C)
Symbol Parameter Min Typ Max Unit
C
IN
Pin capacitance — 2 — pF
V
IH
High-level input voltage 0.75 × VDD
1
— VDD
1
+ 0.3 V
V
IL
Low-level input voltage –0.3 — 0.25 × VDD
1
V
I
IH
High-level input current — — 50 nA
I
IL
Low-level input current — — 50 nA
V
OH
2
High-level output voltage 0.8 × VDD
1
— — V
V
OL
2
Low-level output voltage — — 0.1 × VDD
1
V
I
OH
High-level source current (VDD
1
= 3.3 V,
V
OH
>= 2.64 V, PAD_DRIVER = 3)
— 40 — mA
I
OL
Low-level sink current (VDD
1
= 3.3 V, V
OL
=
0.495 V, PAD_DRIVER = 3)
— 28 — mA
R
P U
Pull-up resistor — 45 — kΩ
R
P D
Pull-down resistor — 45 — kΩ
V
IH_nRST
Chip reset release voltage 0.75 × VDD
1
— VDD
1
+ 0.3 V
V
IL_nRST
Chip reset voltage –0.3 — 0.25 × VDD
1
V
1
VDD is the I/O voltage for a particular power domain of pins.
2
V
OH
and V
OL
are measured using high-impedance load.
4.5 ADC Characteristics
Table 15: ADC Characteristics
Symbol Parameter Min Max Unit
DNL (Differential nonlinearity)
1
ADC connected to an external
–7 7 LSB
100 nF capacitor; DC signal input;
INL (Integral nonlinearity)
ambient temperature at 25 °C;
–12 12 LSB
Wi-Fi off
Sampling rate — — 100 kSPS
2
Effective Range
ATTEN0 0 750 mV
ATTEN1 0 1050 mV
ATTEN2 0 1300 mV
ATTEN3 0 2500 mV
Espressif Systems 32
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ESP32-C3 Series Datasheet v1.2