Datasheet

Table Of Contents
3 Functional Description
support the faster 480 Mbit/s high-speed transfer mode)
programming embedded/external flash
CPU debugging with compact JTAG instructions
a full-speed USB PHY integrated in the chip
3.4.10 TWAI
®
Controller
ESP32-C3 has a TWAI
®
controller with the following features:
compatible with ISO 11898-1 protocol (CAN Specification 2.0)
standard frame format (11-bit ID) and extended frame format (29-bit ID)
bit rates from 1 Kbit/s to 1 Mbit/s
multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)
64-byte receive FIFO
acceptance filter (single and dual filter modes)
error detection and handling: error counters, configurable error interrupt threshold, error code capture,
arbitration lost capture
3.5 Radio and WiFi
ESP32-C3 radio consists of the following blocks:
2.4 GHz receiver
2.4 GHz transmitter
bias and regulators
balun and transmit-receive switch
clock generator
3.5.1 2.4 GHz Receiver
The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to
the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions,
ESP32-C3 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and baseband
filters.
3.5.2 2.4 GHz Transmitter
The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the
antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of
the power amplifier.
Additional calibrations are integrated to cancel any radio imperfections, such as:
carrier leakage
I/Q amplitude/phase matching
baseband nonlinearities
RF nonlinearities
Espressif Systems 24
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ESP32-C3 Series Datasheet v1.2