Datasheet

Product Overview
ESP32-C3 series of SoCs is an ultra-low-power and highly-integrated MCU-based solution that supports 2.4
GHz Wi-Fi and Bluetooth
®
Low Energy (Bluetooth LE). The block diagram of ESP32-C3 is shown below.
Core System
Wireless MAC and
Baseband
Wi-Fi MAC
Wi-Fi
Baseband
Bluetooth LE
Link Controller
Bluetooth LE
Baseband
RISC-V
32-bit
Microprocessor
JTAG
Cache
Peripherals
Espressif’s ESP32-C3 Wi-Fi + Bluetooth
®
Low Energy SoC
ROM
SRAM
USB Serial/
JTAG
GPIO
UART
TWAI
®
General-purpose Timers
I2S
I2C
LED PWM
SPI0/1
RMT
SPI2
DIG ADC
Controller
System Timer
RTC GPIO
Temperature
Sensor
RTC Watchdog Timer
⚙
Modules having power in specific power modes:
Active
Active and Modem-sleep
All modes
Active, Modem-sleep, and Light-sleep; optional in Light-sleep
⚙
GDMA
⚙
Main System Watchdog Timers
2.4 GHz Balun + Switch
2.4 GHz Receiver
2.4 GHz Transmitter
RF Synthesizer
RF
RTC Super Watchdog Timer
eFuse
Controller
Security
Flash
Encryption
RSA
RNG
Digital
Signature
SHA
AES
HMAC
Secure
Boot
RTC
Memory
PMU
RTC
⚙
⚙
⚙
⚙
⚙
⚙
Brownout Detector
Figure 1: Block Diagram of ESP32C3
Solution Highlights
• A complete WiFi subsystem that complies
with IEEE 802.11b/g/n protocol and supports
Station mode, SoftAP mode, SoftAP + Station
mode, and promiscuous mode
• A Bluetooth LE subsystem that supports
features of Bluetooth 5 and Bluetooth mesh
• 32bit RISCV singlecore processor with a
four-stage pipeline that operates at up to 160
MHz
• Stateoftheart power and RF performance
• Storage capacities ensured by 400 KB of
SRAM (16 KB for cache) and 384 KB of ROM on
the chip, and SPI, Dual SPI, Quad SPI, and QPI
interfaces that allow connection to external flash
• Reliable security features ensured by
– Cryptographic hardware accelerators that
support AES-128/256, Hash, RSA, HMAC,
digital signature and secure boot
– Random number generator
– Permission control on accessing internal
Espressif Systems 2
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ESP32-C3 Series Datasheet v1.2