Datasheet
Table Of Contents
- Product Overview
- 1 ESP32-C3 Series Comparison
- 2 Pin Definition
- 3 Functional Description
- 3.1 CPU and Memory
- 3.2 System Clocks
- 3.3 Analog Peripherals
- 3.4 Digital Peripherals
- 3.4.1 General Purpose Input / Output Interface (GPIO)
- 3.4.2 Serial Peripheral Interface (SPI)
- 3.4.3 Universal Asynchronous Receiver Transmitter (UART)
- 3.4.4 I2C Interface
- 3.4.5 I2S Interface
- 3.4.6 Remote Control Peripheral
- 3.4.7 LED PWM Controller
- 3.4.8 General DMA Controller
- 3.4.9 USB Serial/JTAG Controller
- 3.4.10 TWAI® Controller
- 3.5 Radio and Wi-Fi
- 3.6 Bluetooth LE
- 3.7 Low Power Management
- 3.8 Timers
- 3.9 Cryptographic Hardware Accelerators
- 3.10 Physical Security Features
- 3.11 Peripheral Pin Configurations
- 4 Electrical Characteristics
- 5 Package Information
- 6 Related Documentation and Resources
- Revision History
3 Functional Description
3. Functional Description
This chapter describes the functions of ESP32-C3.
3.1 CPU and Memory
3.1.1 CPU
ESP32-C3 has a low-power 32-bit RISC-V single-core microprocessor with the following features:
• four-stage pipeline that supports a clock frequency of up to 160 MHz
• RV32IMC ISA
• 32-bit multiplier and 32-bit divider
• up to 32 vectored interrupts at seven priority levels
• up to 8 hardware breakpoints/watchpoints
• up to 16 PMP regions
• JTAG for debugging
3.1.2 Internal Memory
ESP32-C3’s internal memory includes:
• 384 KB of ROM: for booting and core functions.
• 400 KB of onchip SRAM: for data and instructions, running at a configurable frequency of up to 160
MHz. Of the 400 KB SRAM, 16 KB is configured for cache.
• RTC FAST memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in
Deep-sleep mode.
• 4 Kbit of eFuse: 1792 bits are reserved for your data, such as encryption key and device ID.
• Embedded flash : See details in Chapter 1 ESP32-C3 Series Comparison.
3.1.3 External Flash
ESP32-C3 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external
flash.
CPU’s instruction memory space and read-only data memory space can map into external flash of ESP32-C3,
whose size can be 16 MB at most. ESP32-C3 supports hardware encryption/decryption based on XTS-AES to
protect developers’ programs and data in flash.
Through high-speed caches, ESP32-C3 can support at a time up to:
• 8 MB of instruction memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.
• 8 MB of data memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.
Note:
After ESP32-C3 is initialized, software can customize the mapping of external flash into the CPU address space.
Espressif Systems 17
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ESP32-C3 Series Datasheet v1.2