Datasheet

2 Pin Definition
3.
VDDA,
VDD3P3,
VDD3P3_RTC,
VDD3P3_CPU
CHIP_EN
t
0
t
1
V
IL_nRST
2.8 V
Figure 6: ESP32C3 Powerup and Reset Timing
Table 3: Description of ESP32C3 Powerup and Reset Timing Parameters
Min
Parameter Description (µs)
t
0
Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and
VDD3P3_CPU rails, and activating CHIP_EN
50
t
1
Duration of CHIP_EN signal level < V
IL_nRST
(refer to its value in
Table 14) to reset the chip
50
2.4 Strapping Pins
ESP32-C3 has three strapping pins:
• GPIO2
• GPIO8
• GPIO9
Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG
register. For register description, please refer to Section GPIO Matrix Register Summary in
ESP32-C3 Technical Reference Manual.
During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0”
or ”1”, and hold these bits until the chip is powered down or shut down.
Types of system reset include:
• power-on reset
• RTC watchdog reset
• brownout reset
• analog super watchdog reset
• crystal clock glitch detection reset
By default, GPIO9 is connected to the internal weak pull-up resistor. If GPIO9 is not connected or connected to
an external high-impedance circuit, the latched bit value will be ”1”
Espressif Systems 14
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ESP32-C3 Series Datasheet v1.2