ESP32C3 Series Datasheet UltraLowPower SoC with RISCV SingleCore CPU Supporting IEEE 802.11b/g/n (2.4 GHz WiFi) and Bluetooth® 5 (LE) Including: ESP32-C3 ESP32-C3FN4 ESP32-C3FH4 ESP32-C3FH4AZ Version 1.2 Espressif Systems Copyright © 2022 www.espressif.
Product Overview ESP32-C3 series of SoCs is an ultra-low-power and highly-integrated MCU-based solution that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). The block diagram of ESP32-C3 is shown below. Espressif’s ESP32-C3 Wi-Fi + Bluetooth® Low Energy SoC Wireless MAC and Baseband Core System RISC-V 32-bit Microprocessor Wi-Fi MAC RF 2.4 GHz Balun + Switch Wi-Fi Baseband 2.4 GHz Transmitter Cache SRAM Bluetooth LE Link Controller 2.
• Rich set of peripheral interfaces and GPIOs, memory, external memory, and peripherals ideal for various scenarios and complex – External memory encryption and decryption applications Features WiFi CPU and Memory • 32-bit RISC-V single-core processor, up to 160 • IEEE 802.11 b/g/n-compliant MHz • Supports 20 MHz, 40 MHz bandwidth in 2.4 • CoreMark® score: GHz band – 1 core at 160 MHz: 407.22 CoreMark; 2.
– 2 × 12-bit SAR ADCs, up to 6 channels • Flash encryption – 1 × temperature sensor • 4096-bit OTP, up to 1792 bits for use • Timers: • Cryptographic hardware acceleration: – 2 × 54-bit general-purpose timers – AES-128/256 (FIPS PUB 197) – 3 × watchdog timers • Permission Control – 1 × 52-bit system timer • SHA Accelerator (FIPS PUB 180-4) • RSA Accelerator Low Power Management • Random Number Generator (RNG) • Power Management Unit with four power modes • HMAC • Digital signature Security • S
Contents Contents Product Overview 2 Solution Highlights 2 Features 3 Applications 4 1 ESP32C3 Series Comparison 9 1.1 ESP32-C3 Series Nomenclature 9 1.2 Comparison 9 2 Pin Definition 10 2.1 Pin Layout 10 2.2 Pin Description 11 2.3 Power Scheme 13 2.4 Strapping Pins 14 3 Functional Description 17 3.1 17 3.2 3.3 3.4 CPU and Memory 3.1.1 CPU 17 3.1.2 Internal Memory 17 3.1.3 External Flash 17 3.1.4 Address Mapping Structure 18 3.1.
Contents 3.6 3.5.4 Wi-Fi Radio and Baseband 25 3.5.5 Wi-Fi MAC 25 3.5.6 Networking Features 26 Bluetooth LE 26 3.6.1 Bluetooth LE Radio and PHY 26 3.6.2 Bluetooth LE Link Layer Controller 26 3.7 Low Power Management 27 3.8 Timers 27 3.9 3.8.1 General Purpose Timers 27 3.8.2 System Timer 27 3.8.3 Watchdog Timers 28 Cryptographic Hardware Accelerators 28 3.10 Physical Security Features 28 3.11 Peripheral Pin Configurations 28 4 Electrical Characteristics 31 4.
List of Tables List of Tables 1 ESP32-C3 Series Comparison 2 Pin Description 11 3 Description of ESP32-C3 Power-up and Reset Timing Parameters 14 4 Strapping Pins 15 5 Parameter Descriptions of Setup and Hold Times for the Strapping Pins 16 6 IO MUX Pin Functions 20 7 Power-Up Glitches on Pins 21 8 Mapping of SPI Signals and Chip Pins 22 9 Connection Between ESP32-C3 and External Flash 22 10 Peripheral Pin Configurations 29 11 Absolute Maximum Ratings 31 12 Recommended Oper
List of Figures List of Figures 1 Block Diagram of ESP32-C3 2 2 ESP32-C3 Series Nomenclature 9 3 ESP32-C3 Pin Layout (Top View, Excluding ESP32-C3FH4AZ) 10 4 ESP32-C3FH4AZ Pin Layout (Top View) 11 5 ESP32-C3 Power Scheme 13 6 ESP32-C3 Power-up and Reset Timing 14 7 Setup and Hold Times for the Strapping Pins 15 8 Address Mapping Structure 18 9 QFN32 (5×5 mm) Package 41 Espressif Systems 8 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.
1 ESP32-C3 Series Comparison 1. ESP32C3 Series Comparison 1.1 ESP32C3 Series Nomenclature ESP32-C3 H F x AZ Other Identification Code Flash Flash temperature H: High temperature N: Normal temperature Flash Chip series Figure 2: ESP32C3 Series Nomenclature 1.2 Comparison Table 1: ESP32C3 Series Comparison Ordering Code ESP32-C3 1 ESP32-C3FN4 ESP32-C3FH4 ESP32-C3FH4AZ 2 Embedded Flash Ambient Temperature (°C) Package (mm) GPIO No.
2 Pin Definition 2. Pin Definition 25 GPIO18 26 GPIO19 27 U0RXD 28 U0TXD 29 XTAL_N 30 XTAL_P 31 VDDA 32 VDDA 2.
25 GPIO18 26 GPIO19 27 U0RXD 28 U0TXD 29 XTAL_N 30 XTAL_P 31 VDDA 32 VDDA 2 Pin Definition LNA_IN 1 24 NC VDD3P3 2 23 NC VDD3P3 3 22 NC XTAL_32K_P 4 21 NC XTAL_32K_N 5 20 NC GPIO2 6 CHIP_EN 7 GPIO3 8 ESP32-C3FH4AZ 19 NC 18 VDD_SPI 17 VDD3P3_CPU GPIO10 16 GPIO9 15 GPIO8 14 MTDO 13 MTCK 12 VDD3P3_RTC 11 MTMS 9 MTDI 10 33 GND Figure 4: ESP32C3FH4AZ Pin Layout (Top View) 2.2 Pin Description Table 2: Pin Description Name No.
2 Pin Definition Name No.
2 Pin Definition 2.3 Power Scheme ESP32-C3 has four input power pins: • VDDA1 • VDDA2 • VDD3P3_RTC • VDD3P3_CPU And one input/output power pin: • VDD_SPI VDDA1 and VDDA2 are the input power supply for the analog domain. When working as an output power supply, VDD_SPI can be powered by VDD3P3_CPU via RSP I (nominal 3.3 V). VDD_SPI can be powered off via software to minimize the current leakage of flash in Deep-sleep mode. RTC IO is powered from VDD3P3_RTC.
2 Pin Definition 3. t0 t1 2.8 V VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU VIL_nRST CHIP_EN Figure 6: ESP32C3 Powerup and Reset Timing Table 3: Description of ESP32C3 Powerup and Reset Timing Parameters Min Parameter t0 t1 Description (µs) Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and VDD3P3_CPU rails, and activating CHIP_EN Duration of CHIP_EN signal level < VIL_nRST (refer to its value in Table 14) to reset the chip 50 50 2.
2 Pin Definition To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-C3. After reset, the strapping pins work as normal-function pins. Table 4 lists detailed booting configurations of the strapping pins.
2 Pin Definition Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pins Min Parameter Description t0 Setup time before CHIP_EN goes from low to high 0 t1 Hold time after CHIP_EN goes high 3 Espressif Systems (ms) 16 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.
3 Functional Description 3. Functional Description This chapter describes the functions of ESP32-C3. 3.1 CPU and Memory 3.1.1 CPU ESP32-C3 has a low-power 32-bit RISC-V single-core microprocessor with the following features: • four-stage pipeline that supports a clock frequency of up to 160 MHz • RV32IMC ISA • 32-bit multiplier and 32-bit divider • up to 32 vectored interrupts at seven priority levels • up to 8 hardware breakpoints/watchpoints • up to 16 PMP regions • JTAG for debugging 3.1.
3 Functional Description 3.1.4 Address Mapping Structure Figure 8: Address Mapping Structure Note: The memory space with gray background is not available for use. 3.1.5 Cache ESP32-C3 has an eight-way set associative cache. This cache is read-only and has the following features: • size: 16 KB • block size: 32 bytes • pre-load function • lock function • critical word first and early restart Espressif Systems 18 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.
3 Functional Description 3.2 System Clocks 3.2.1 CPU Clock The CPU clock has three possible sources: • external main crystal clock • fast RC oscillator (typically about 17.5 MHz, and adjustable) • PLL clock The application can select the clock source from the three clocks above. The selected clock source drives the CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock source would be the external main crystal clock divided by 2.
3 Functional Description 3.4 Digital Peripherals 3.4.1 General Purpose Input / Output Interface (GPIO) ESP32-C3 has 22 or 16 GPIO pins which can be assigned various functions by configuring corresponding registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC. All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are configured as an input, the input value can be read by software through the register.
3 Functional Description Reset The default configuration of each pin after reset: • 0 - input disabled, in high impedance state (IE = 0) • 1 - input enabled, in high impedance state (IE = 1) • 2 - input enabled, pull-down resistor enabled (IE = 1, WPD = 1) • 3 - input enabled, pull-up resistor enabled (IE = 1, WPU = 1) • 4 - output enabled, pull-up resistor enabled (OE = 1, WPU = 1) • 0* - input disabled, pull-up resistor enabled (IE = 0, WPU = 0, USB_WPU = 1).
3 Functional Description MHz in STR mode. • SPI2 Generalpurpose SPI (GPSPI) mode When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master and slave modes. The host’s clock frequency is configurable. Data are transferred in unit of byte. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA.
3 Functional Description • fast mode (400 Kbit/s) • up to 800 Kbit/s (constrained by SCL and SDA pull-up strength) • 7-bit and 10-bit addressing mode • double addressing mode • 7-bit broadcast address You can configure instruction registers to control the I2C interface for more flexibility. 3.4.5 I2S Interface ESP32-C3 includes a standard I2S interface.
3 Functional Description support the faster 480 Mbit/s high-speed transfer mode) • programming embedded/external flash • CPU debugging with compact JTAG instructions • a full-speed USB PHY integrated in the chip 3.4.10 TWAI® Controller ESP32-C3 has a TWAI® controller with the following features: • compatible with ISO 11898-1 protocol (CAN Specification 2.
3 Functional Description • antenna matching These built-in calibration routines reduce the cost, time, and specialized equipment required for product testing. 3.5.3 Clock Generator The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators and dividers. The clock generator has built-in calibration and self-test circuits.
3 Functional Description • 802.11mc FTM 3.5.6 Networking Features Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocols over Wi-Fi. TLS 1.0, 1.1 and 1.2 is also supported. 3.6 Bluetooth LE ESP32-C3 includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and Bluetooth mesh. 3.6.
3 Functional Description 3.7 Low Power Management With the use of advanced power-management technologies, ESP32-C3 can switch between different power modes. • Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen. • Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wi-Fi base band, Bluetooth LE base band, and radio are disabled, but Wi-Fi and Bluetooth LE connection can remain active. • Light-sleep mode: The CPU is paused.
3 Functional Description 3.8.3 Watchdog Timers ESP32-C3 contains three watchdog timers: one in each of the two timer groups (called Main System Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT). During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order to detect and recover from booting errors. Watchdog timers have the following features: • four stages, each with a programmable timeout value.
3 Functional Description Table 10: Peripheral Pin Configurations Interface Signal Pin Function ADC ADC1_CH0 XTAL_32K_P Two 12-bit SAR ADCs ADC1_CH1 XTAL_32K_N ADC1_CH2 GPIO2 ADC1_CH3 GPIO3 ADC1_CH4 MTMS ADC2_CH0 MTDI MTDI MTDI MTCK MTCK MTMS MTMS MTDO MTDO U0RXD_in Any GPIO pins JTAG UART JTAG for software debugging U0CTS_in Two UART channels with hardware flow control and GDMA U0DSR_in U0TXD_out U0RTS_out U0DTR_out U1RXD_in U1CTS_in U1DSR_in U1TXD_out U1RTS_out U1DTR_out I
3 Functional Description Interface Signal Pin Function Any GPIO pins Two channels for an IR transceiver of various I2SO_SD1_out Remote Control RMT_SIG_IN0~1 Peripheral RMT_SIG_OUT0~1 SPI0/1 SPICLK_out_mux SPICLK Support Standard SPI, Dual SPI, Quad SPI, and SPICS0_out SPICS0 QPI that allow connection to external flash SPICS1_out Any GPIO pins SPID_in/_out SPID SPIQ_in/_out SPIQ SPIWP_in/_out SPIWP SPIHD_in/_out SPIHD FSPICLK_in/_out_mux Any GPIO pins SPI2 waveforms SPI, Quad
4 Electrical Characteristics 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the device. These are stress ratings only, and do not refer to the functional operation of the device. Table 11: Absolute Maximum Ratings Symbol VDDA, Parameter VDD3P3, VDD3P3_RTC, Min Voltage applied to power supply pins VDD3P3_CPU, VDD_SPI per power domain TST ORE Storage temperature Max Unit –0.3 3.
4 Electrical Characteristics Note: In real-life applications, when VDD_SPI works in 3.3 V output mode, VDD3P3_CPU may be affected by RSP I . For example, when VDD3P3_CPU is used to drive a 3.3 V flash, it should comply with the following specifications: VDD3P3_CPU > VDD_flash_min + I_flash_max*RSP I Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the maximum current. For more information, please refer to section 2.3 Power Scheme. 4.4 DC Characteristics (3.
4 Electrical Characteristics 1 To get better DNL results, you can sample multiple times and apply a filter, or calculate the average value. 2 kSPS means kilo samples-per-second. 4.6 Current Consumption The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF port. All transmitters’ measurements are based on a 100% duty cycle. Table 16: Current Consumption Depending on RF Modes Work mode Description TX Active (RF working) RX Peak (mA) 802.
4 Electrical Characteristics Table 18 – cont’d from previous page Test Item Test Conditions Test Standard 1 ESD (Electro-Static HBM (Human Body Mode) ± 2000 V Discharge Sensitivity) JS-001 2 CDM (Charge Device Mode) ± 1000 V JS-002 Current trigger ± 200 mA Latch up JESD78 Voltage trigger 1.
4 Electrical Characteristics Table 21: TX EVM Test Rate Min Typ SL1 (dB) (dB) (dB) 802.11b, 1 Mbps, @21 dBm — –24.5 –10 802.11b, 11 Mbps, @21 dBm — –25.0 –10 802.11g, 6 Mbps, @21 dBm — –23.0 –5 802.11g, 54 Mbps, @19 dBm — –27.5 –25 802.11n, HT20, MCS0, @20 dBm — –22.5 –5 802.11n, HT20, MCS7, @18.5 dBm — –29.0 –27 802.11n, HT40, MCS0, @20 dBm — –22.5 –5 802.11n, HT40, MCS7, @18.5 dBm — –28.0 –27 1 SL stands for standard limit value. 4.8.
4 Electrical Characteristics Table 22 – cont’d from previous page Min Typ Max (dBm) (dBm) (dBm) 802.11n, HT40, MCS5 — –74.6 — 802.11n, HT40, MCS6 — –73.0 — 802.11n, HT40, MCS7 — –71.4 — Rate Table 23: Maximum RX Level Min Typ Max (dBm) (dBm) (dBm) 802.11b, 1 Mbps — 5 — 802.11b, 11 Mbps — 5 — 802.11g, 6 Mbps — 5 — 802.11g, 54 Mbps — 0 — 802.11n, HT20, MCS0 — 5 — 802.11n, HT20, MCS7 — 0 — 802.11n, HT40, MCS0 — 5 — 802.
4 Electrical Characteristics 4.9.1 Bluetooth LE RF Transmitter (TX) Specifications Table 26: Transmitter Characteristics Bluetooth LE 1 Mbps Parameter Description Min RF power control range RF transmit power Carrier frequency offset and drift Modulation characteristics In-band spurious emissions Typ Max Unit –27.00 0 18.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 17.00 — kHz Max |f0 − fn | — 1.75 — kHz Max |fn − fn−5 | — 1.46 — kHz |f1 − f0 | — 0.
4 Electrical Characteristics Table 28 – cont’d from previous page Parameter Description Min Unit 250.00 — kHz — 235.00 — kHz ± 2 MHz offset — –37.90 — dBm ± 3 MHz offset — –41.00 — dBm > ± 3 MHz offset — –42.50 — dBm Min ∆ f 1max (for at least 99.
4 Electrical Characteristics Table 30 – cont’d from previous page Parameter Description Out-of-band blocking performance Intermodulation Min Typ Max Unit 30 MHz ~ 2000 MHz — –5 — dBm 2003 MHz ~ 2399 MHz — –18 — dBm 2484 MHz ~ 2997 MHz — –15 — dBm 3000 MHz ~ 12.75 GHz — –5 — dBm — — –30 — dBm Table 31: Receiver Characteristics Bluetooth LE 2 Mbps Parameter Description Sensitivity @30.8% PER — — –93 — dBm Maximum received signal @30.
4 Electrical Characteristics Table 32 – cont’d from previous page Parameter Description Image frequency — — –40 — dB F = Fimage + 1 MHz — –50 — dB F = Fimage – 1 MHz — –37 — dB Adjacent channel to image frequency Min Typ Max Unit Table 33: Receiver Characteristics Bluetooth LE 500 Kbps Parameter Description Sensitivity @30.8% PER — — –100 — dBm Maximum received signal @30.
5 Package Information 5. Package Information Figure 9: QFN32 (5×5 mm) Package Note: • For the source file of recommended PCB land pattern (dxf), you can view it with Autodesk Viewer; • For information about tape, reel, and product marking, please refer to Espressif Chip Packaging Information. Espressif Systems 41 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.
6 Related Documentation and Resources 6. Related Documentation and Resources Related Documentation • ESP32-C3 Technical Reference Manual – Detailed information on how to use the ESP32-C3 memory and peripherals. • Certificates http://espressif.com/en/support/documents/certificates • Documentation Updates and Update Notification Subscription http://espressif.
Revision History Revision History Date Version Release Notes • Added a new chip variant ESP32-C3FH4AZ; 2022-04-13 v1.2 • Updated Figure Block Diagram of ESP32-C3; • Added the wake up source for Deep-sleep mode in Section 3.7 Low Power Management. • Updated Figure Block Diagram of ESP32-C3 to show power modes; • Added CoreMark score in Features; • Updated Table Pin Description to show default pin functions; 2021-10-26 v1.
Revision History Date Version Release Notes • Clarified that of the 400 KB SRAM, 16 KB is configured as cache; 2021-01-18 v0.6 • Updated maximum value to standard limit value in Table TX EVM Test in Section 4.8.1 Wi-Fi RF Transmitter (TX) Specifications. • Updated information about Wi-Fi; • Added connection between embedded flash ports and chip pins to table notes in Section 2.
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