Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
Electrical characteristics STM32WLE5J8/JB/JC
88/135 DS13105 Rev 4
Table 49. Low-power mode wakeup timings
(1)
Symbol Parameter Conditions Typ Max Unit
t
WUSLEEP
Wakeup time from
Sleep to Run mode
- 0.188 0.222
N° of
CPU
cycles
t
WULPSLEEP
Wakeup time from
LPSleep to LPRun
mode
Wakeup in Flash with memory in power-down
during LPSleep mode (FPDS = 1 in PWR_CR1)
and with clock MSI = 2 MHz
3.81 4.38
t
WUSTOP0
Wakeup time from
Stop 0 mode in Flash
memory
(2)
To Run mode
(Range 1)
Wakeup clock MSI = 48 MHz 2.14 2.90
µs
Wakeup clock MSI = 16 MHz 2.78 3.58
Wakeup clock HSI16 = 16 MHz 1.99 TBD
Wakeup clock HSI16 = 16 MHz
with HSIKERON enabled
1.01 1.13
Wakeup clock MSI = 4 MHz 6.79 8.21
Wakeup clock MSI = 2 MHz 10.4 12.2
To LPRun mode Wakeup clock MSI = 2 MHz 10.5 12.3
t
WUSTOP1
Wakeup time from
Stop 1 mode in Flash
memory
(2)
To Run mode
(Range 1)
Wakeup clock MSI = 48 MHz 5.15 6.55
µs
Wakeup clock MSI = 16 MHz 5.73 7.14
Wakeup clock HSI16 = 16 MHz 5.71 7.10
Wakeup clock HSI16 = 16 MHz
with HSIKERON enabled
4.57 6.52
Wakeup clock MSI = 4 MHz 8.43 9.93
Wakeup clock MSI = 2 MHz 11.9 13.7
To LPRun mode Wakeup clock MSI = 2 MHz 10.6 13.9
t
WUSTOP2
Wakeup time from
Stop 2 mode in Flash
memory
(2)
To Run mode
(Range 1)
Wakeup clock MSI = 48 MHz 5.56 6.85
µs
Wakeup clock MSI = 16 MHz 6.32 7.59
Wakeup clock HSI16 = 16 MHz 6.28 7.51
Wakeup clock HSI16 = 16 MHz
with HSIKERON enabled
6.26 7.53
Wakeup clock MSI = 4 MHz 9.69 10.9
Wakeup clock MSI = 2 MHz 14.0 15.4
To LPRun mode Wakeup clock MSI = 2 MHz 10.5 13.8
t
WUSTBY
Wakeup time from
Standby to Run mode
Range 1
Wakeup clock MSI = 4 MHz 34.3 39.2
µs
Wakeup clock MSI = 8 MHz 22.4 25.6
t
WUSHUTD
Wakeup time from
Shutdown to Run mode
Range 1 Wakeup clock MSI = 4 MHz 264 316
1. Guaranteed by characterization results (V
DD
= 3 V, T = 25 °C).
2. Wakeup time is equivalent when code is executed from SRAM1 compared to Flash memory. It is also equivalent when
going to Range 2 rather than Range 1.