Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
Electrical characteristics STM32WLE5J8/JB/JC
70/135 DS13105 Rev 4
V
BOR0
(2)
Brownout reset threshold 0
Rising edge 1.62 1.66 1.70
V
Falling edge 1.60 1.64 1.69
V
BOR1
Brownout reset threshold 1
Rising edge 2.06 2.10 2.14
Falling edge 1.96 2.00 2.04
V
BOR2
Brownout reset threshold 2
Rising edge 2.26 2.31 2.35
Falling edge 2.16 2.20 2.24
V
BOR3
Brownout reset threshold 3
Rising edge 2.56 2.61 2.66
Falling edge 2.47 2.52 2.57
V
BOR4
Brownout reset threshold 4
Rising edge 2.85 2.90 2.95
Falling edge 2.76 2.81 2.86
V
PVD0
Programmable voltage detector threshold 0
Rising edge 2.10 2.15 2.19
Falling edge 2.00 2.05 2.10
V
PVD1
PVD threshold 1
Rising edge 2.26 2.31 2.36
Falling edge 2.15 2.20 2.25
V
PVD2
PVD threshold 2
Rising edge 2.41 2.46 2.51
Falling edge 2.31 2.36 2.41
V
PVD3
PVD threshold 3
Rising edge 2.56 2.61 2.66
V
Falling edge 2.47 2.52 2.57
V
PVD4
PVD threshold 4
Rising edge 2.69 2.74 2.79
Falling edge 2.59 2.64 2.69
V
PVD5
PVD threshold 5
Rising edge 2.85 2.91 2.96
Falling edge 2.75 2.81 2.86
V
PVD6
PVD threshold 6
Rising edge 2.92 2.98 3.04
Falling edge 2.84 2.90 2.96
V
hyst_BORH0
Hysteresis voltage of BORH0
Hysteresis in
continuous mode
-20-
mV
Hysteresis in
other mode
-30-
V
hyst_BOR_PVD
Hysteresis voltage of BORH (except
BORH0) and PVD
- - 100 -
I
DD
(BOR_PVD)
(2)
BOR
(3)
(except BOR0) and PVD
consumption from V
DD
- - 1.1 1.6 µA
V
PVM3
V
DDA
peripheral voltage monitoring
Rising edge 1.61 1.65 1.69
V
Falling edge 1.6 1.64 1.68
V
hyst_PVM3
PVM3 hysteresis - - 10 - mV
I
DD
(PVM3)
(2)
PVM3 consumption from V
DD
--2-µA
Table 33. Embedded reset and power-control block characteristics (continued)
Symbol Parameter Conditions
(1)
Min Typ Max Unit