Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
DS13105 Rev 4 65/135
STM32WLE5J8/JB/JC Electrical characteristics
127
Table 28. Sub-GHz radio general specifications
Symbol Description Conditions Min Typ Max Unit
FR Frequency synthesizer range Low-power PA 150 - 960 MHz
FSTEP Frequency synthesizer step High-resolution mode HSE / 2
(2)(5)
-095 - Hz
PHN
(1)(2)
Synthesizer phase noise
(868 to 915 MHz)
100 kHz offset - –100 -
dBc/Hz1 MHz offset - –120 -
10 MHz offset - –135 -
TS_FS Synthesizer wakeup time From Standby, HSE32 mode - 40 -
µs
TS_HOP Synthesizer hop time 10 MHz step - 40 -
TS_OSC Crystal oscillator wakeup time
From Standby, RC
(3)
normal mode
from HSE32 off
-170 -
OSC_
TRM
Crystal oscillator trimming range
for crystal frequency error
compensation
(4)
Min/max XTAL specifications ±15 ±30 - ppm
BR_F Bitrate, FSK
Programmable
(min modulation index is 0.5)
0.6 - 300
(5)
Kbit/s
FDA Frequency deviation, FSK
Programmable
(FDA + BR_F/2 250 kHz)
0.6 - 200 kHz
BR_L Bitrate, LoRa
Min for SF12, BW_L = 7.8 kHz
Max for SF7, BW_L = 500 kHz
0.018 - 62.5
(6)
Kbit/s
BW_L Signal BW, LoRa Programmable 7.8 - 500
(6)
kHz
SF Spreading factor for LoRa
Programmable,
chips/symbol = 2
SF
5-12 -
1. Phase Noise specifications are given for the recommended PLL bandwidth to be used for the specific modulation/BR,
optimized settings may be used for specific applications.
2. Phase Noise is not constant over frequency, due to the topology of the PLL. For two frequencies close to each other, the
phase noise may change significantly
3. Wakeup time till crystal oscillator frequency is within ±10 ppm.
4. OSC_TRIM is the available trimming range to compensate for crystal initial frequency error and to allow crystal temperature
compensation implementation. The total available trimming range is higher and allows the compensation for all device
process variations
5. Maximum bit rate is assumed to scale with the RF frequency: for example 300 Kbit /s in the 869-to-915 MHz frequency band
and only 50 Kbit/s at 150 MHz.
6. For RF frequencies below 400 MHz, there is a scaling between the frequency and supported bandwidth. Some bandwidths
may not be available below 400 MHz.