Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
Electrical characteristics STM32WLE5J8/JB/JC
62/135 DS13105 Rev 4
5.3.3 Sub-GHz radio characteristics
Electrical characteristics of the sub-GHz radio are given with the following conditions unless
otherwise specified:
• V
DD
= 3.3 V. The current consumption is measured as described in Figure 12.
I
DD
includes current consumption of all supplies (V
DDRF
, V
DDSMPS
, V
DD
, V
DDA
, V
BAT
).
All peripherals except Sub-GHz radio are disabled and the system is in Standby mode.
• Temperature = 25 °C
• HSE32 = 32 MHz
• F
RF
= 434/868/915 MHz
• All RF impedances matched using reference design
• Reference design implementing a 32 MHz crystal oscillator
• Transmit mode output power defined in 50 load
• FSK BER (bit error rate) = 0.1 %, 2-level FSK modulation without pre-filtering,
BR = 4.8 Kbit/s, FDA = 5 kHz, BW_F = 20 kHz
• LoRa PER (packet error rate) = 1 %, packet of 64 bytes, preamble of 8 bytes, error
correction code CR = 4/5, CRC on payload enabled, no reduced encoding, no implicit
header
• Sensitivities given using highest LNA gain step
• Power consumption measured with -140 dBm signal and AGC ON
• Blocking immunity, ACR and co-channel rejection, given for a single tone interferer and
referenced to sensitivity +6 dB, blocking tests performed with unmodulated signal
• Bandwidth expressed on DSB (double-sided band)
P
D
Power dissipation at
T
A
= 85 °C for suffix 6
version
(4)
UFBGA73 - 392.0 mW
T
A
Ambient temperature for
suffix 6 version
Maximum power
dissipation
–40
85
°C
Low-power dissipation
(5)
105
T
J
Junction temperature range Suffix 6 version –40 105 °C
1. When the reset is released, the functionality is guaranteed down to V
BOR0
min.
2. This formula has to be applied only on the power supplies related to the I/O structure described in Table 19:
STM32WLE5J8/JB/JC pin definition. Maximum I/O input voltage is the smallest value between min (V
DD
, V
DDA
) + 3.6 V
and 5.5 V.
3. For operation with voltage higher than min (V
DD
, V
DDA
) + 0.3 V, the internal pull-up and pull-down resistors must be
disabled.
4. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
J
max (see Table 92: Package thermal
characteristics).
5. In low-power dissipation state, T
A
can be extended to this range, as long as T
J
does not exceed T
J
max (see Table 92:
Package thermal characteristics).
Table 25. General operating conditions (continued)
Symbol Parameter Conditions Min Max Unit