Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
DS13105 Rev 4 49/135
STM32WLE5J8/JB/JC Pinouts, pin description and alternate functions
56
G2 PC6 I/O FT - I2S2_MCK, CM4_EVENTOUT -
D6 PA0 I/O FT_a -
TIM2_CH1, I2C3_SMBA,
I2S_CKIN, USART2_CTS,
COMP1_OUT, TIM2_ETR,
CM4_EVENTOUT
TAMP_IN2/WKUP1
G3 PA1 I/O FT_a -
TIM2_CH2, LPTIM3_OUT,
I2C1_SMBA, SPI1_SCK,
USART2_RTS, LPUART1_RTS,
CM4_EVENTOUT
-
H2 PA2 I/O FT_a -
LSCO, TIM2_CH3, USART2_TX,
LPUART1_TX, COMP2_OUT,
DEBUG_PWR_LDORDY,
CM4_EVENTOUT
LSCO
H1 PA3 I/O FT_a -
TIM2_CH4, I2S2_MCK,
USART2_RX, LPUART1_RX,
CM4_EVENTOUT
-
G5 VSS S - - - -
H5 VDD S - - - -
J1 PA4 I/O FT -
RTC_OUT2, LPTIM1_OUT,
SPI1_NSS, USART2_CK,
DEBUG_SUBGHZSPI_
NSSOUT, LPTIM2_OUT,
CM4_EVENTOUT
-
J2 PA5 I/O FT -
TIM2_CH1, TIM2_ETR,
SPI2_MISO, SPI1_SCK,
DEBUG_SUBGHZSPI_
SCKOUT, LPTIM2_ETR,
CM4_EVENTOUT
-
F4 PA6 I/O FT -
TIM1_BKIN, I2C2_SMBA,
SPI1_MISO, LPUART1_CTS,
DEBUG_SUBGHZSPI_
MISOOUT, TIM16_CH1,
CM4_EVENTOUT
-
H3 PA7 I/O FT_fa -
TIM1_CH1N, I2C3_SCL,
SPI1_MOSI, COMP2_OUT,
DEBUG_SUBGHZSPI_
MOSIOUT, TIM17_CH1,
CM4_EVENTOUT
-
J3 PA8 I/O FT_a -
MCO, TIM1_CH1,
SPI2_SCK/I2S2_CK,
USART1_CK, LPTIM2_OUT,
CM4_EVENTOUT
-
Table 19. STM32WLE5J8/JB/JC pin definition (continued)
Pin
number
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional functions
UFBGA73