Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
DS13105 Rev 4 35/135
STM32WLE5J8/JB/JC Functional overview
46
• The RTC clock is derived (selected by software) from one of the following sources:
– LSE clock
– LSI clock
– HSE32 clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• The IWDG clock is always the LSI clock.
The RCC feeds the CPU system timer (SysTick) external clock with the AHB clock (HCLK1)
divided by eight. The SysTick can work either with this clock or directly with the CPU clock
(HCLK1), configurable in the SysTick control and status register.
FCLK1 acts as CPU free-running clock. For more details, refer to the programming manual
STM32 Cortex
®
-M4 MCUs and MPUs programming manual (PM0214).
Figure 7. Clock tree
1. For full details about the internal and external clock source characteristics, refer to the electrical characteristics section in
the device datasheet.
2. The ADC clock can additionally be derived from the AHB clock of the ADC bus interface, divided by a programmable factor
(1, 2 or 4). When the programmable factor is 1, the AHB prescaler must be equal to 1.
MSv62605V2
LSI RCC 32 kHz
LSE OSC
32.768 kHz
LSCO
to IWDG
OSC_IN
OSC_OUT
MCO
/1 - 16
/32
LSE CSS
PLL
/P
/R
/Q
/M
SYSCLK
MSI
MSI
HSI16
HSI16
HSE32
HSE32
PLLRCLK
PLLRCLK
LSE
LSI
SYS clock
source
control
SYSCLK
MSI
HSI16
AHB3
SHDHPRE
/1,2,...,512
HCLK1
HCLK3
APB1
PPRE1
/1,2,4,8,16
to CPU, AHB1, AHB2
to CPU FCLK
/8
to CPU system timer
APB2
PPRE2
/1,2,4,8,16
PCLK1
PCLK2
to AHB3, Flash, SRAM1, SRAM2
to APB1 TIMx
to APB2 TIMx
to USART1 to LPTIM1
to LPUART1
to ADC
to RTC
x1 or
x2
x1 or
x2
to I2C1
PCLKn
SYSCLK
HSI16
HSI16
HSI16
PCLKn
LSI
LSE
PLLPCLK
SYSCLK
PCLKn
LSE
to APB2
to APB1
to RF
SYSCLK
MSI
to RNG
PLLQCLK
PLLRCLK
OSC32_IN
OSC32_OUT
LSI
LSE
LSI
LSE
HSEPRE
/1,2
x
N
to I2C2
to I2C3
to LPTIM3
to LPTIM2
PCLK3 to APB3
to USART2
HSI16
to SPI2S2
I2S_CKIN
HSI16
PLLPCLK
PLLQCLK
CPU
HPRE
/1,2,...,512
HSE32 OSC
32 MHz
HSE CSS
MSI RC
100 kHz - 48 MHz
HSI16 RC
16 MHz
LSI DAC