Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
DS13105 Rev 4 27/135
STM32WLE5J8/JB/JC Functional overview
46
wakeup time but a higher consumption compared with Stop 2.
In Stop 0 mode, the main regulator remains on, resulting in the fastest wakeup time but
with much higher consumption. The active peripherals and wakeup sources are the
same as in Stop 1 mode that uses the low-power regulator.
The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz
or HSI16, depending on the software configuration.
• Stop 2 mode: part of the V
CORE
domain is powered off. Only SRAM1, SRAM2, CPU
and some peripherals preserve their contents (see Table 7).
All clocks in the V
CORE
domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
LSI and LSE can be kept running.
RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The sub-
GHz radio may also remain active independent from the CPU.
Some peripherals with the wakeup capability can enable HSI16 RC during the Stop 2
mode to detect their wakeup condition (see Table 7).
The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or
HSI16, depending on the software configuration.
• Standby mode: V
CORE
domain is powered off. However, it is possible to preserve the
SRAM2 content as detailed below:
– Standby mode with SRAM2 retention when the RRS bit is set in the PWR control
register 3 (PWR_CR3). In this case, SRAM2 is supplied by the low-power
regulator.
– Standby mode when the RRS bit is cleared in the PWR control register 3
(PWR_CR3). In this case the main regulator and the low-power regulator are
powered off.
All clocks in the V
CORE
domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.
LSI and LSE can be kept running.
Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The
sub-GHz radio and the PVD may also remain active when enabled independent from
the CPU. In Standby mode, the PVD selects its lowest level.
The system clock, when exiting Standby modes, is MSI at 4 MHz.
• Shutdown mode: V
CORE
domain is powered off. All clocks in the V
CORE
domain are
stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The
system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the
supply voltage monitoring is disabled and the product behavior is not guaranteed in
case of a power voltage drop.