Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
Functional overview STM32WLE5J8/JB/JC
26/135 DS13105 Rev 4
The voltage regulators are always enabled after a reset. Depending on the application
modes, the V
CORE
supply is provided either by the main regulator or by the low-power
regulator (LPR).
When MR is used, a dynamic voltage scaling is proposed to optimize power as follows:
• range 1: high-performance range
The system clock frequency can be up to 48 MHz. The Flash memory access time for
read access is minimum. Write and erase operations are possible.
• range 2: low-power range
The system clock frequency can be up to 16 MHz.The Flash memory access time for a
read access is increased as compared to range 1. Write and erase operations are
possible.
3.9.4 VBAT operation
The VBAT pin is used to power the device VBAT domain (RTC, LSE and backup registers)
from an external battery, an external super-capacitor, or from V
DD
when no external battery
nor an external super-capacitor are present. Three anti-tamper detection pins are available
in VBAT mode.
VBAT operation is automatically activated when V
DD
is not present.
An internal V
BAT
battery charging circuit is embedded and can be activated when V
DD
is
present.
Note: When the microcontroller is supplied only from V
BAT
, external interrupts and RTC
alarm/events do not exit it from VBAT operation.
3.10 Low-power modes
The devices support several low-power modes to achieve the best compromise between
low-power consumption, short startup time, available peripherals and available wakeup
sources.
By default, the microcontroller is in Run mode, range 1, after a system or a power-on reset.
It is up to the user to select one of the low-power modes described below:
• Sleep mode: CPU clock off, all peripherals including CPU core peripherals (among
them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event
occurs.
• Low-power run mode (LPRun): when the system clock frequency is reduced below
2 MHz. The code is executed from the SRAM or from the Flash memory. The regulator
is in low-power mode to minimize the operating current.
• Low-power sleep mode (LPSleep): entered from the LPRun mode.
• Stop 0 and Stop 1 modes: the content of SRAM1, SRAM2 and of all registers is
retained. All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32
are disabled. LSI and LSE can be kept running.
RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz
radio may remain active independently from the CPU.
Some peripherals with the wakeup capability can enable HSI16 RC during the Stop
mode to detect their wakeup condition.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller