Datasheet

DS13105 Rev 4 25/135
STM32WLE5J8/JB/JC Functional overview
46
The SMPS needs a clock to be functional. If for any reason this clock stops, the device may
be destroyed. To avoid this situation, a clock detection is used to, in case of a clock failure,
switch off the SMPS and enable the LDO. The SMPS clock detection is enabled by the sub-
GHz radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled
and must be enabled before enabling the SMPS.
Danger: Before enabling the SMPS, the SMPS clock detection must be
enabled in the sub-GHz radio SUBGHZ_SMPSC0R.CLKDE.
3.9.2 Power supply supervisor
The devices integrate a power-on reset/power-down reset, coupled with a Brownout reset
(BOR) circuitry.
BOR0 level cannot be disabled. Other BOR levels can be enabled by user option. When
enabled, BOR is active in all power modes except in Shutdown
Five BOR thresholds can be selected through option bytes.
During power-on, BOR keeps the device under reset until the supply voltage V
DD
reaches
the specified V
BORx
threshold:
• When V
DD
drops below the selected threshold, a device reset is generated.
• When V
DD
is above the V
BORx
upper limit, the device reset is released and the system
can start.
The devices feature an embedded PVD (programmable voltage detector) that monitors the
V
DD
power supply and compares it with the V
PVD
threshold. An interrupt can be generated
when V
DD
drops below the V
PVD
threshold and/or when V
DD
is higher than the V
PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state.
The PVD is enabled by software and can be configured to monitor the V
DD
supply level
needed for the sub-GHz radio operation. For this, the PVD must select its lowest threshold,
and the PVD and the wakeup must be enabled by the EWPVD bit in PWR_CR3 register.
Only a voltage drop below the PVD level generates a wakeup event.
In addition, the devices embed a PVM (peripheral voltage monitor) that compares the
independent supply voltage V
DDA
with a fixed threshold to ensure that the peripheral is in its
functional supply range.
Finally, a radio end-of-life monitor provides information on the V
DD
supply when V
DD
is too
low to operate the sub-GHz radio. When reaching the EOL level, the software must stop all
radio activity in a safe way.
3.9.3 Linear voltage regulator
Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the Backup domain. The main regulator (MR) output voltage (VCORE)
can be programmed by software to two different power ranges (range 1 and range 2), to
optimize the consumption depending on the system maximum operating frequency.