Datasheet
Table Of Contents
- Table 1. Device summary
- 1 Introduction
- 2 Description
- 3 Functional overview
- 3.1 Architecture
- 3.2 Arm Cortex-M4 core
- 3.3 Adaptive real-time memory accelerator (ART Accelerator)
- 3.4 Memory protection unit (MPU)
- 3.5 Memories
- 3.6 Security memory management
- 3.7 Boot modes
- 3.8 Sub-GHz radio
- 3.9 Power supply management
- 3.10 Low-power modes
- 3.11 Peripheral interconnect matrix
- 3.12 Reset and clock controller (RCC)
- 3.13 General-purpose inputs/outputs (GPIOs)
- 3.14 Directly memory access controller (DMA)
- 3.15 Interrupts and events
- 3.16 Analog-to-digital converter (ADC)
- 3.17 Voltage reference buffer (VREFBUF)
- 3.18 Digital-to-analog converter (DAC)
- 3.19 Comparator (COMP)
- 3.20 True random number generator (RNG)
- 3.21 Advanced encryption standard hardware accelerator (AES)
- 3.22 Public key accelerator (PKA)
- 3.23 Timer and watchdog
- 3.24 Real-time clock (RTC), tamper and backup registers
- 3.25 Inter-integrated circuit interface (I2C)
- 3.26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 3.27 Low-power universal asynchronous receiver transmitter (LPUART)
- 3.28 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)
- 3.29 Development support
- 4 Pinouts, pin description and alternate functions
- 5 Electrical characteristics
- 5.1 Parameter conditions
- 5.2 Absolute maximum ratings
- 5.3 Operating conditions
- 5.3.1 Main performances
- 5.3.2 General operating conditions
- 5.3.3 Sub-GHz radio characteristics
- Table 26. Sub-GHz radio power consumption
- Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON)
- Table 28. Sub-GHz radio general specifications
- Table 29. Sub-GHz radio receive mode specifications
- Table 30. Sub-GHz radio transmit mode specifications
- Table 31. Sub-GHz radio power management specifications
- 5.3.4 Operating conditions at power-up/power-down
- 5.3.5 Embedded reset and power-control block characteristics
- 5.3.6 Embedded voltage reference
- 5.3.7 Supply current characteristics
- Typical and maximum current consumption
- Table 35. Current consumption in Run and LPRun modes, CoreMark code with data running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 36. Current consumption in Run and LPRun modes, CoreMark code with data running from SRAM1
- Table 37. Typical current consumption in Run and LPRun modes, with different codes running from Flash memory, ART enable (cache ON, prefetch OFF)
- Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1
- Table 39. Current consumption in Sleep and LPSleep modes, Flash memory ON
- Table 40. Current consumption in LPSleep mode, Flash memory in power-down
- Table 41. Current consumption in Stop 2 mode
- Table 42. Current consumption in Stop 1 mode
- Table 43. Current consumption in Stop 0 mode
- Table 44. Current consumption in Standby mode
- Table 45. Current consumption in Shutdown mode
- Table 46. Current consumption in VBAT mode
- Table 47. Current under Reset condition
- I/O system current consumption
- On-chip peripheral current consumption
- Typical and maximum current consumption
- 5.3.8 Wakeup time from low-power modes and voltage scaling transition times
- 5.3.9 External clock source characteristics
- 5.3.10 Internal clock source characteristics
- 5.3.11 PLL characteristics
- 5.3.12 Flash memory characteristics
- 5.3.13 EMC characteristics
- 5.3.14 Electrical sensitivity characteristics
- 5.3.15 I/O current injection characteristics
- 5.3.16 I/O port characteristics
- 5.3.17 NRST pin characteristics
- 5.3.18 Analog switches booster
- 5.3.19 Analog-to-digital converter characteristics
- 5.3.20 Temperature sensor characteristics
- 5.3.21 VBAT monitoring characteristics
- 5.3.22 Voltage reference buffer characteristics
- 5.3.23 Digital-to-analog converter characteristics
- 5.3.24 Comparator characteristics
- 5.3.25 Timers characteristics
- 5.3.26 Communication interfaces characteristics
- 6 Package information
- 6.1 UFBGA73 package information
- Figure 26. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array package outline
- Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data
- Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint
- Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA)
- Device marking for UFBGA73
- 6.2 Package thermal characteristics
- 6.1 UFBGA73 package information
- 7 Ordering information
- 8 Revision history
Functional overview STM32WLE5J8/JB/JC
22/135 DS13105 Rev 4
3.9 Power supply management
The devices embed two different regulators: one LDO and one DC/DC (SMPS). The SMPS
can be optionally switched-on by software to improve the power efficiency. As LDO and
SMPS operate in parallel, the SMPS switch-on is transparent to the user and only the power
efficiency is affected.
3.9.1 Power supply schemes
The devices require a V
DD
operating voltage supply between 1.8 V and 3.6 V. Several
independent supplies (V
DDSMPS
, V
FBSMPS
, V
DDA
, V
DDRF
) can be provided for specific
peripherals:
• V
DD
= 1.8 V to 3.6 V
V
DD
is the external power supply for the I/Os, the system analog blocks such as reset,
power management, internal clocks and low-power regulator. It is provided externally
through VDD pins.
• V
DDSMPS
= 1.8 V to 3.6 V
V
DDSMPS
is the external power supply for the SMPS step-down converter. It is provided
externally through VDDSMPS supply pin and must be connected to the same supply as
V
DD
.
• V
FBSMPS
= 1.45 V to 1.62 V (1.55 V typical)
V
FBSMPS
is the external power supply for the main system regulator. It is provided
externally through VFBSMPS pin and is supplied through the SMPS step-down
converter.
• V
DDA
= 0 V to 3.6 V (DAC/COMPs minimum voltage is 1.71 V, ADC minimum voltage is
1.8 V and VREFBUF minimum voltage is 2.4 V).
V
DDA
is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, and comparators. The V
DDA
voltage level is independent from the V
DD
voltage (see power-up and power-down limitations below) and must preferably be
connected to V
DD
when these peripherals are not used.
• V
DDRF
= 1.8 V to 3.6 V
V
DDRF
is an external power supply for the radio. It is provided externally through the
VDDRF pin and must be connected to the same supply as V
DD
.
• V
DDRF1V5
= 1.45 V to 1.62 V
V
DDRF1V5
is an external power supply for the radio. It is provided externally through the
VDDRF1V5 pin and must be connected externally to VFBSMPS.
• V
BAT
= 1.55 V to 3.6 V
V
BAT
is the power supply for RTC, TAMP, external clock 32 kHz oscillator and backup
registers (through power switch) when V
DD
is not present.
LORA_BW_15 15.63 250
LORA_BW_10 10.42 167
LORA_BW_7 7.81 250
Table 6. LoRa mode intermediate frequencies (continued)
Setting name Bandwidth (kHz) f
if
(kHz)