Datasheet

Functional overview STM32WLE5J8/JB/JC
14/135 DS13105 Rev 4
3 Functional overview
3.1 Architecture
The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller
subsystem using an Arm Cortex-M4 (called CPU).
An RF low-layer stack is needed and is to be run on CPU with the host application code.
The RF subsystem communication is done through an internal SPI interface.
3.2 Arm Cortex-M4 core
The Arm Cortex-M4 is a processor for embedded systems. It has been developed to provide
a low-cost platform that meets the needs of MCU implementation, with a reduced pin count
and low-power consumption, while delivering outstanding computational performance and
an advanced response to interrupts.
The Arm Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an Arm core in the memory size usually associated
with 8- and 16-bit devices.
This processor supports a set of DSP instructions that allow efficient signal processing and
complex algorithm execution.
With its embedded Arm core, the STM32WLE5J8/JB/JC devices are compatible with all
Arm tools and software.
Figure 1 shows the general block diagram of the STM32WLE5J8/JB/JC devices.
3.3 Adaptive real-time memory accelerator (ART Accelerator)
The ART Accelerator is a memory accelerator that is optimized for STM32 industry-
standard Arm Cortex-M4 processor. The ART Accelerator balances the inherent
performance advantage of the Arm Cortex-M4 over Flash memory technologies, that
normally require the processor to wait for the Flash memory at higher frequencies.
To release the processor near 60 DMIPS performance at 48 MHz, the ART Accelerator
implements an instruction prefetch queue and branch cache, that increases the program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 48 MHz.
3.4 Memory protection unit (MPU)
The memory protection unit (MPU) is used to manage the CPU accesses to memory, to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to eight protected areas that can in turn be
divided up into eight subareas. The protection area sizes are between 32 bytes and the
whole 4 Gbytes of addressable memory.