Datasheet

Table Of Contents
DS13105 Rev 4 127/135
STM32WLE5J8/JB/JC Electrical characteristics
127
JTAG/SWD characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, f
PCLKx
frequency and supply voltage conditions
summarized in Table 25: General operating conditions, with the following configuration:
capacitive load C = 30 pF
measurement done at CMOS levels: 0.5 x V
DD.
Refer to Section 5.3.16: I/O port characteristics for more details.
Table 88. Dynamic JTAG characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
PP
1/t
c(TCK)
TCK clock frequency
2.7 V < V
DD
< 3.6 V - - 33
MHz
1.8 V < V
DD
< 3.6 V - - 25
ti
su(TMS)
TMS input setup time - 0.5 - -
ns
ti
h(TMS)
TMS input hold time - 1 - -
ti
su(TDI)
TDI input setup time - 1 - -
ti
h(TDI)
TDI input hold time - 2.5 - -
tov
(TDO)
TDO output valid time
2.7 V < V
DD
< 3.6 V - 12 15
1.8 V< V
DD
< 3.6 V - 12 20
toh
(TDO)
TDO output hold time - 10 - -
Table 89. Dynamic SWD characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
PP
1/t
c(SWCLK)
SWCLK clock frequency
2.7 V < V
DD
< 3.6 V - - 58
MHz
1.8 < V
DD
< 3.6 V - - 41
ti
su(SWDIO)
SWDIO input setup time - 1 - -
ns
ti
h(SWDIO)
SWDIO input hold time - 2 - -
tov
(SWDIO)
SWDIO output valid time
2.7 V < V
DD
< 3.6 V - 15 17
1.8 V < V
DD
< 3.6 V - 15 24
toh
(SWDIO)
SWDIO output hold time - 9 - -