Datasheet

Electrical characteristics STM32WLE5J8/JB/JC
118/135 DS13105 Rev 4
Figure 22. 12-bit buffered/non-buffered DAC
I
DDA(DAC)
DAC consumption from
V
DDA
DAC output
buffer ON
No load, middle
code (0x800)
- 315 500
µA
No load, worst code
(0xF1C)
- 450 670
DAC output
buffer OFF
No load, middle
code (0x800)
--0.2
Sample and hold mode, C
SH
=
100 nF
-
315 x
T
on
/(T
on
+T
off
)
(4)
670 x
T
on
/(T
on
+T
off
)
(4)
I
DDV(DAC)
DAC consumption from
V
REF+
DAC output
buffer ON
No load, middle
code (0x800)
- 185 240
µA
No load, worst code
(0xF1C)
- 340 400
DAC output
buffer OFF
No load, middle
code (0x800)
- 155 205
Sample and hold mode, buffer ON,
C
SH
= 100 nF, worst case
-
185 x
T
on
/(T
on
+T
off
)
(4)
400 x
T
on
/(T
on
+T
off
)
(4)
Sample and hold mode, buffer OFF,
C
SH
= 100 nF, worst case
-
155 x
T
on
/(T
on
+T
off
)
(4)
205 x
T
on
/(T
on
+T
off
)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 67: I/O static characteristics.
4. T
on
is the Refresh phase duration. T
off
is the Hold phase duration. Refer to the reference manual for more details.
Table 79. DAC characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
MSv47959V2
12-bit
digital-to-analog
converter
Buffered/non-buffered DAC
DAC_OUTx
R
LOAD
C
LOAD
Buffer
(1)
(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads
directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in
the DAC_CR register.