Datasheet

DS13105 Rev 4 117/135
STM32WLE5J8/JB/JC Electrical characteristics
127
t
SETTLING
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes, when
DAC_OUT reaches final
value ±0.5 LSB, ±1 LSB,
±2 LSB, ±4 LSB, ±8 LSB)
Normal mode
DAC output
buffer ON
CL  50 pF
RL  5 k
±0.5 LSB - 1.7 3
µs
±1 LSB - 1.6 2.9
±2 LSB - 1.55 2.85
±4 LSB - 1.48 2.8
±8 LSB - 1.4 2.75
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-22.5
t
WAKEUP
(2)
Wakeup time from off state
(setting the ENx bit in the
DAC control register) until
final value ±1 LSB
Normal mode DAC output buffer ON
CL  50 pF, RL  5 k
-4.27.5
µs
Normal mode DAC output buffer
OFF, CL  10 pF
-25
PSRR V
DDA
supply rejection ratio
Normal mode DAC output buffer ON
CL  50 pF, RL  5 k, DC
--80-28dB
T
W_to_W
Minimum time between two
consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
DAC_MCR:MODEx[2:0] = 000 or 001
CL  50 pF, RL  5 k
1--
µs
DAC_MCR:MODEx[2:0] = 010 or 011
CL  10 pF
1.4 - -
t
SAMP
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
DAC_OUT pin
connected
DAC output buffer
ON, C
SH
= 100 nF
-0.73.5
ms
DAC output buffer
OFF, C
SH
= 100 nF
- 10.5 18
DAC_OUT pin
not connected
(internal
connection
only)
DAC output buffer
OFF
-23.5µs
I
leak
Output leakage current
Sample and hold mode,
DAC_OUT pin connected
---
(3)
nA
CI
int
Internal sample and hold
capacitor
-5.278.8pF
t
TRIM
Middle code offset trim time DAC output buffer ON 50 - - µs
V
offset
Middle code offset for 1 trim
code step
V
REF+
= 3.6 V - 1500 -
µV
V
REF+
= 1.8 V - 750 -
Table 79. DAC characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit