Datasheet

DS13105 Rev 4 113/135
STM32WLE5J8/JB/JC Electrical characteristics
127
Figure 20. ADC accuracy characteristics
Figure 21. Typical connection diagram using the ADC
1. Refer to Table 72: ADC characteristics for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance
(refer to Table 67: I/O static characteristics for the value of the pad capacitance). A high C
parasitic
value downgrades the
conversion accuracy. To remedy this, f
ADC
must be reduced.
3. Refer to Table 67: I/O static characteristics for the values of Ilkg.
General PCB design guidelines
Power supply decoupling must be performed as shown in Figure 11: Power supply scheme.
The 100 nF capacitor must be ceramic (good quality) and must be placed as close as
possible to the chip.
MSv19880V3
(1) Example of an actual transfer curve
(2) Ideal transfer curve
(3) End point correlation line
4095
4094
4093
7
6
5
4
3
2
1
0
2 345 6
1 7 4093 4094 4095
E
D
1 LSB
ideal
(1)
(3)
(2)
E
L
E
T
E
G
E
O
Code
(V
AIN
/ V
REF+
)*4095
E
T
total unadjusted error: maximum deviation
between the actual and ideal transfer curves.
E
G
gain error: deviation between the last ideal
transition and the last actual one.
E
D
differential linearity error: maximum deviation
between actual steps and the ideal ones.
E
L
integral linearity error: maximum deviation between
any actual transition and the end point correlation line.
E
O
offset error: maximum deviation between the
first actual transition and the first ideal one.
MS33900V5
Sample and hold ADC converter
12-bit
converter
C
parasitic
(2)
I
lkg
(3)
V
T
C
ADC
V
DDA
R
AIN
(1)
V
AIN
V
T
AINx
R
ADC