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DS13105 Rev 4 107/135
STM32WLE5J8/JB/JC Electrical characteristics
127
Figure 19. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in the above table.
Otherwise the reset is not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.18 Analog switches booster
Table 70. NRST pin characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
NRST input low level voltage - - - 0.3 x V
DD
V
V
IH(NRST)
NRST input high level voltage - 0.7 x V
DD
--
V
hys(NRST)
NRST Schmitt trigger voltage hysteresis - - 200 - mV
R
PU
Weak pull-up equivalent resistor
(2)
V
IN
= V
SS
25 40 55 k
V
F(NRST)
NRST input, filtered pulse - - - 70
ns
V
NF(NRST)
NRST input, not filtered pulse 1.8 V V
DD
3.6 V 350 - -
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10 %)
.
MS19878V3
R
PU
V
DD
Internal reset
External
reset circuit
(1)
NRST
(2)
Filter
0.1 μF
Table 71. Analog switches booster characteristics
(1)
Symbol Parameter Min Typ Max Unit
V
DD
Supply voltage 1.8 - 3.6 V
t
SU(BOOST)
Booster startup time - - 240 µs
I
DD(BOOST)
Booster consumption for 1.8 V V
DD
2.0 V - - 250
µABooster consumption for 2.0 V V
DD
2.7 V - - 500
Booster consumption for 2.7 V V
DD
3.6 V - - 900
1. Guaranteed by design.