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Table Of Contents

This is information on a product in full production.

February 2020 DS13105 Rev 4 1/135

STM32WLE5J8 STM32WLE5JB

STM32WLE5JC

Multiprotocol LPWAN 32-bit Arm

Cortex

-M4 MCUs, LoRa

(G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM

Datasheet - production data

Features

• Radio

– Frequency range: 150 MHz to 960 MHz

– Modulation: LoRa

, (G)FSK, (G)MSK and

BPSK

– RX sensitivity:

–125 dBm for 2-FSK

(at 1.2 Kbit/s),

–148 dBm for LoRa

(at 10.4 kHz, spreading factor 12)

– Transmitter high output power,

programmable up to +22 dBm

– Transmitter low output power,

programmable up to +15 dBm

– Compliant with the following radio

frequency regulations: ETSI EN 300 220,

EN 300 113, EN 301 166, FCC CFR 47

Part 15, 24, 90, 101 and the Japanese

ARIB STD-T30, T-67, T-108

• Ultra-low-power platform

– 1.8 V to 3.6 V power supply

–

–40 °C to +85 °C temperature range

– Shutdown mode: 31 nA (V

= 3 V)

– Standby (+ RTC) mode:

360 nA (V

= 3 V)

– Stop2 (+ RTC) mode: 1.07 µA (V

= 3 V)

– Active-mode MCU: < 72 µA/MHz

(CoreMark

)

– Active-mode RX: 4.82 mA

– Active-mode TX: 15 mA at 10 dBm and

87 mA at 20 dBm (LoRa

125 kHz)

• Core: 32-bit Arm

Cortex

-M4 CPU

– Adaptive real-time accelerator (ART

Accelerator) allowing 0-wait-state

execution from Flash memory, frequency

up to 48 MHz, MPU and DSP instructions

– 1.25 DMIPS/MHz (Dhrystone 2.1)

• Security and identification

– Hardware encryption AES 256-bit

– True random number generator (RNG)

– Sector protection against read/write

operations (PCROP, RDP, WRP)

– CRC calculation unit

– Unique device identifier (64-bit UID

compliant with IEEE 802-2001 standard)

– 96-bit unique die identifier

– Hardware public key accelerator (PKA)

• Supply and reset management

– High-efficiency embedded SMPS step

down converter

– SMPS to LDO smart switch

– Ultra-safe, low-power BOR (brownout

reset) with 5 selectable thresholds

– Ultra-low-power POR/PDR

– Programmable voltage detector (PVD)

–V

BAT

mode with RTC and 20x32-byte

backup registers

• Clock sources

– 32 MHz crystal oscillator

– TCXO support: programmable supply

voltage

– 32 kHz oscillator for RTC with calibration

– High-speed internal 16 MHz factory

trimmed RC (± 1%)

– Internal low-power 32 kHz RC

– Internal multi-speed low-power 100 kHz to

48 MHz RC

– PLL for CPU, ADC and audio clocks

• Memories

– Up to 256-Kbyte Flash memory

– Up to 64-Kbyte RAM

– 20x32-bit backup register

UFBGA73

(5x5 mm)

www.st.com

Summary of content (135 pages)

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STM32WLE5J8 STM32WLE5JB STM32WLE5JC Multiprotocol LPWAN 32-bit Arm®Cortex®-M4 MCUs, LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM Datasheet - production data Features • Radio – Frequency range: 150 MHz to 960 MHz – Modulation: LoRa®, (G)FSK, (G)MSK and BPSK – RX sensitivity: –125 dBm for 2-FSK (at 1.2 Kbit/s), –148 dBm for LoRa® (at 10.
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STM32WLE5J8/JB/JC – Bootloader supporting USART and SPI interfaces – OTA (over-the-air) firmware update capable – Sector protection against read/write operations • Rich analog peripherals (down to 1.62 V) – 12-bit ADC 2.5 Msps, up to 16-bit with hardware oversampling, conversion range up to 3.
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STM32WLE5J8/JB/JC Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.
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Contents STM32WLE5J8/JB/JC 3.16 3.15.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37 3.15.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 37 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.16.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.16.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . .
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STM32WLE5J8/JB/JC 6 Contents 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3 Operating conditions . . . . . . . . . . . . . . . .
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Contents STM32WLE5J8/JB/JC 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32WLE5J8/JB/JC List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . .
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93.
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STM32WLE5J8/JB/JC List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. STM32WLE5J8/JB/JC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 sub-GHz radio system block diagram . . . . .
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Introduction 1 STM32WLE5J8/JB/JC Introduction This document provides information on the STM32WLE5J8/JB/JC microcontrollers. For information on the Arm®(a)Cortex®-M4 core, refer to the Cortex®-M4 Technical Reference Manual available from the www.arm.com website. For information on LoRa®, refer to the Semtech website (https://www.semtech.com/technology/lora).
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STM32WLE5J8/JB/JC Description The devices also feature the standard and advanced communication interfaces listed below: • two USART (supporting LIN, smartcard, IrDA, modem control and ISO7816) • one low-power UART (LPUART) • three I2C (SMBus/PMBus) • two SPIs (up to 16 MHz, one supporting I2S) • semaphores for processor firmware process synchronization The operating temperature/voltage ranges are –40 °C to +85 °C from a 1.8 V to 3.6 V power supply.
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Description STM32WLE5J8/JB/JC Table 2. Main features and peripheral counts (continued) Feature STM32WLE5JCI6 STM32WLE5JBI6 DMA (7 channels) 2 Semaphores 1 Security AES 256 bits 1 RNG 1 PKA 1 PCROP, RDP, WRP 1 CRC 1 64-bit UID compliant with IEEE 802-2001 standard 1 96-bit die ID 1 Tamper pins 3 Wakeup pins 3 GPIOs 43 ADC (number of channels, ext + int) 1 (12 + 4) DAC (number of channels) 1 (1) Internal VREF Yes Analog comparator 2 Operating voltage 1.8 to 3.
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STM32WLE5J8/JB/JC Description SUBGHZ SPI Figure 1. STM32WLE5J8/JB/JC block diagram Sub-GHz radio Flash interface arbiter + ART Accelerator memory 256-Kbyte Flash JTAG/SWD SRAM2 LDO/SMPS HSE32 32 MHz backup memory RTC TAMP LSE 32 kHz Backup domain IWDG LSI 32 kHz PLL SRAM1 AHB3 NVIC Cortex-M4 (DSP) ≤ 48 MHz RCC HSI 1 % 16 MHz MSI 5 % 0.
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Functional overview STM32WLE5J8/JB/JC 3 Functional overview 3.1 Architecture The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller subsystem using an Arm Cortex-M4 (called CPU). An RF low-layer stack is needed and is to be run on CPU with the host application code. The RF subsystem communication is done through an internal SPI interface. 3.2 Arm Cortex-M4 core The Arm Cortex-M4 is a processor for embedded systems.
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STM32WLE5J8/JB/JC Functional overview The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
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Functional overview STM32WLE5J8/JB/JC Table 3. Access status versus RDP level and execution mode (continued) Area Read Backup registers SRAM2 Debug, boot from SRAM or boot from system memory (loader) User execution RDP level Write Erase Read Write Erase No No NA(2) 1 Yes Yes NA(2) 2 Yes Yes NA NA NA NA No No No(2) NA NA NA 1 Yes Yes Yes(2) 2 Yes Yes Yes 1. The option byte can be modified by the sub-GHz radio. 2. Erased when RDP changes from Level 1 to Level 0.
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STM32WLE5J8/JB/JC 3.6 Functional overview Security memory management The devices contain many security blocks both for the sub-GHz MAC layer and the Host application, such as: • true random number generator (RNG) • advance encryption standard hardware accelerators (128- and 256-bit AES, supporting ECB, CBC, CTR, GCM, GMAC and CCM chaining modes) • private key acceleration (PKA): • 3.
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Functional overview 3.8.2 STM32WLE5J8/JB/JC General description The sub-GHz radio provides an internal processing unit to handle communication with the system CPU. Communication is handled by commands sent over the SPI interface, and a set of interrupts is used to signal events. BUSY information signals operation activity and is used to indicate when the sub-GHz radio commands cannot be received. The block diagram of the sub-GHz radio system is shown in the figure below. Figure 2.
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STM32WLE5J8/JB/JC Functional overview For this, the REG PA must be supplied directly from VDD on VDDSMPS pin, as shown in the figure below. The output power range is programmable in 32 steps of ~ 1 dB. The power amplifier ramping timing is also programmable.This allows adaptation to meet radio regulation requirements. Figure 3. High output power PA SMPS mode LDO mode VDD VDD VDDSMPS (1.8 to 3.6V) VDDSMPS (1.8 to 3.6V) VLXSMPS VLXSMPS LDO/SMPS LDO/SMPS VFBSMPS (1.55V) VFBSMPS (1.
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Functional overview STM32WLE5J8/JB/JC Figure 4. Low output power PA LDO mode SMPS mode VDD VDD VDDSMPS (1.8 to 3.6V) VDDSMPS (1.8 to 3.6V) VLXSMPS VLXSMPS LDO/SMPS LDO/SMPS VFBSMPS (1.55V) VFBSMPS (1.55V) VDDPA VDDPA VR_PA (up to 1.35V) REG PA VR_PA (up to 1.35V) REG PA RFO_LP RFO_LP LP PA LP PA Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil between VLXSMPS and VFBSMPS pins. 3.8.
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STM32WLE5J8/JB/JC 3.8.6 Functional overview Intermediate frequencies The sub-GHz radio receiver operates mostly in low-IF configuration, except for specific highbandwidth settings. Table 5. FSK mode intermediate frequencies Setting name Bandwidth (kHz) RX_BW_467 467.0 RX_BW_234 234.3 RX_BW_117 117.3 RX_BW_58 58.6 RX_BW_29 29.3 RX_BW_14 14.6 RX_BW_7 7.3 RX_BW_373 373.6 RX_BW_187 187.2 RX_BW_93 93.8 RX_BW_46 46.9 RX_BW_23 23.4 RX_BW_11 11.7 RX_BW_5 5.8 RX_BW_312 312.
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Functional overview STM32WLE5J8/JB/JC Table 6. LoRa mode intermediate frequencies (continued) 3.9 Setting name Bandwidth (kHz) fif (kHz) LORA_BW_15 15.63 250 LORA_BW_10 10.42 167 LORA_BW_7 7.81 250 Power supply management The devices embed two different regulators: one LDO and one DC/DC (SMPS). The SMPS can be optionally switched-on by software to improve the power efficiency.
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STM32WLE5J8/JB/JC • Functional overview VREF-, VREF+ VREF+ is the input reference voltage for ADC. It is also the output of the internal voltage reference buffer when enabled. – When VDDA < 2 V, VREF+ must be equal to VDDA. – When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. VREF+ can be grounded when ADC is not active. The internal voltage reference buffer supports the following output voltages, configured with VRS bit in the VREFBUF_CSR register: – VREF+ around 2.048 V: this requires VDDA ≥ 2.
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Functional overview STM32WLE5J8/JB/JC The different supply configurations are shown in the figure below. Figure 6.
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STM32WLE5J8/JB/JC Functional overview The SMPS needs a clock to be functional. If for any reason this clock stops, the device may be destroyed. To avoid this situation, a clock detection is used to, in case of a clock failure, switch off the SMPS and enable the LDO. The SMPS clock detection is enabled by the subGHz radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled and must be enabled before enabling the SMPS. Danger: 3.9.
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Functional overview STM32WLE5J8/JB/JC The voltage regulators are always enabled after a reset. Depending on the application modes, the VCORE supply is provided either by the main regulator or by the low-power regulator (LPR). When MR is used, a dynamic voltage scaling is proposed to optimize power as follows: • range 1: high-performance range The system clock frequency can be up to 48 MHz. The Flash memory access time for read access is minimum. Write and erase operations are possible.
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STM32WLE5J8/JB/JC Functional overview wakeup time but a higher consumption compared with Stop 2. In Stop 0 mode, the main regulator remains on, resulting in the fastest wakeup time but with much higher consumption. The active peripherals and wakeup sources are the same as in Stop 1 mode that uses the low-power regulator. The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration.
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Functional overview STM32WLE5J8/JB/JC The table below summarizes the peripheral features over all available modes. Wakeup capability is detailed in gray cells. Table 7.
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STM32WLE5J8/JB/JC Functional overview Table 7.
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Functional overview STM32WLE5J8/JB/JC 7. HSE32 can be used by sub-GHz radio system. 8. USART reception is functional in Stop 0 and Stop 1 modes. LPUART1 reception is functional is Stop 0, Stop 1, and Stop 2 modes. LPUART1 generates a wakeup interrupt on Start address match or received frame event. 9. I2Cx (x= 1, 2) address detection is functional in Stop 0 and Stop 1 modes. I2C3 address detection is functional in Stop 0, Stop 1 and Stop 2 modes. I2C3 generates a wakeup interrupt in case of address match.
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STM32WLE5J8/JB/JC Functional overview Table 8.
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Functional overview STM32WLE5J8/JB/JC 2. When retaining SRAM2 in Standby mode, the MCU uses the low-power regulator (LPR) mode. 3. When the CPU is in Shutdown mode, the sub-GHz radio cannot be activated and is forced in Deep-sleep mode. 3.10.1 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is "analog state" (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.
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STM32WLE5J8/JB/JC Functional overview Table 10.
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Functional overview STM32WLE5J8/JB/JC Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following: • • The clock used for true RNG, is derived (selected by software) from one of the following sources: – PLL VCO (PLLQCLK) (only available in Run mode) – MSI (only available in Run mode) – LSI clock – LSE clock The ADC clock is derived (selected by software) from one of the following sources: – system clock (SYSCLK) (only available in Run mode) – HSI16 clock (only av
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STM32WLE5J8/JB/JC • Functional overview The RTC clock is derived (selected by software) from one of the following sources: – LSE clock – LSI clock – HSE32 clock divided by 32 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE. • The IWDG clock is always the LSI clock. The RCC feeds the CPU system timer (SysTick) external clock with the AHB clock (HCLK1) divided by eight.
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Functional overview 3.13 STM32WLE5J8/JB/JC General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.
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STM32WLE5J8/JB/JC Functional overview 3.15 Interrupts and events 3.15.1 Nested vectored interrupt controller (NVIC) The devices embed an NIVC able to manage 16 priority levels, and to handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M4.
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Functional overview STM32WLE5J8/JB/JC The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers. 3.16.1 Temperature sensor The temperature sensor (TS) generates a VTS voltage that varies linearly with temperature. The temperature sensor is internally connected to the ADC VIN[12] input channel, to convert the sensor output voltage into a digital value.
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STM32WLE5J8/JB/JC 3.17 Functional overview Voltage reference buffer (VREFBUF) The devices embed a voltage reference buffer that can be used as voltage reference for ADC, and also as voltage reference for external components through the VREF+ pin. VREFBUF supports two voltages: 2.048 V and 2.5 V. An external voltage reference can be provided through the VREF+ pin when VREFBUF is off. 3.
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Functional overview 3.21 STM32WLE5J8/JB/JC Advanced encryption standard hardware accelerator (AES) The AES encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in FIPS (federal information processing standards) publication 197. Multiple chaining modes are supported (ECB, CBC, CTR, GCM, GMAC, CCM), for key sizes of 128 or 256 bits.
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STM32WLE5J8/JB/JC Functional overview The four independent channels can be used for: • input capture • output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0 - 100 %) • one-pulse mode output In debug mode, the TIM1 counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose timers (described in the next section) using the same architecture.
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Functional overview STM32WLE5J8/JB/JC LPTIM1/2/3 main features: 3.23.
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STM32WLE5J8/JB/JC Functional overview The RTC is functional in VBAT mode. Twenty 32-bit backup registers are retained in all low-power modes and also in VBAT mode. These registers can be used to store sensitive data as their content is protected by a tamper detection circuit. Three tamper pins and four internal tampers are available for anti-tamper detection. The external tamper pins can be configured for edge or level detection with or without filtering. 3.
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Functional overview STM32WLE5J8/JB/JC Table 15. I2C implementation (continued) I2C features(1) Wakeup from Stop mode I2C1(2) X SMBus/PMBus (3) X I2C2(2) (3) X I2C3 X(4) X X 1. X = supported. 2. The register content is lost in Stop 2 mode. 3. Wakeup supported from Stop 0 and Stop 1 modes. 4. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes. 3.
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STM32WLE5J8/JB/JC Functional overview The LPUART has a clock domain independent from the CPU clock, and can wake up the system from Stop mode using baudrates up to 220 Kbaud. The wakeup events from Stop mode are programmable and can be one of the following: • start bit detection • any received data frame • a specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud.
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Functional overview STM32WLE5J8/JB/JC this case, it provides the communication clock (SCK) to the external slave device. The SPI interface can also operate in multimaster configuration. The I2S protocol is also a synchronous serial communication interface. It can operate in slave or master mode with half-duplex communication. It can address four different audio standards including the Philips I2S standard, the MSB- and LSB-justified standards and the PCM standard. Table 17.
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STM32WLE5J8/JB/JC 4 Pinouts, pin description and alternate functions Pinouts, pin description and alternate functions Figure 8.
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Pinouts, pin description and alternate functions STM32WLE5J8/JB/JC C2 PB3 PB4 I/O I/O FT_a FT_fa Notes C1 Pin name (function after reset) I/O structure UFBGA73 Pin number Pin type Table 19.
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STM32WLE5J8/JB/JC Pinouts, pin description and alternate functions D6 G3 PC6 I/O PA0 PA1 I/O I/O Notes G2 Pin name (function after reset) I/O structure UFBGA73 Pin number Pin type Table 19.
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Pinouts, pin description and alternate functions STM32WLE5J8/JB/JC PA9 I/O Notes E5 Pin name (function after reset) I/O structure UFBGA73 Pin number Pin type Table 19.
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STM32WLE5J8/JB/JC Pinouts, pin description and alternate functions D8 E6 PB1 I/O PB2 PB12 I/O I/O Notes E7 Pin name (function after reset) I/O structure UFBGA73 Pin number Pin type Table 19.
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Pinouts, pin description and alternate functions STM32WLE5J8/JB/JC Table 19.
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 SYS_ AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2S2 TIM1/ LPTIM3 I2C1/ I2C2/ I2C3 SPI1/ SPI2S2 RF USART1 / USART2 LPUART1 - - PA0 - TIM2_ CH1 - - I2C3_ SMBA I2S_ CKIN - USART2_ CTS - - PA1 - TIM2_ CH2 - LPTIM3_ OUT I2C1_ SMBA SPI1_ SCK - USART2_ RTS LPUART1_ RTS PA2 LSCO TIM2_ CH3 - - - - - USART2_ TX PA3 - TIM2_ CH4 - - - I2S2_ MCK - PA4 RTC_ OUT2 LPTIM1 _OUT - - - SPI1_ NSS PA5 - TIM2_ CH1 TIM2_ ETR SPI2_ MIS
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AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_ AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2S2 TIM1/ LPTIM3 I2C1/ I2C2/ I2C3 PA12 - TIM1_ ETR - LPTIM3_ IN1 PA13 JTMSSWDIO - - PA14 JTCKSWCLK LPTIM1_ OUT PA15 JTDI PB0 Port A (continued) DS13105 Rev 4 Port B AF9 AF10 AF11 SPI1/ SPI2S2 RF USART1 / USART2 LPUART1 - - I2C2_ SCL SPI1_ MOSI RF_BUSY USART1_ RTS - - - I2C2_ SMBA - - - IR_OUT - - I2C1_ SMBA - - - TIM2_ CH1 TIM2_ ETR - I2C2_ SDA SPI1_ NSS - - - - - - -
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AF0 AF1 AF2 AF3 AF4 AF5 SYS_ AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2S2 TIM1/ LPTIM3 I2C1/ I2C2/ I2C3 PB11 - TIM2_ CH4 - - PB12 - TIM1_ BKIN - PB13 - TIM1_ CH1N PB14 - PB15 - Port B (continued) Port AF7 AF8 AF9 AF10 AF11 SPI1/ SPI2S2 RF USART1 / USART2 LPUART1 - - I2C3_ SDA - - - LPUART1_ TX - TIM1_ BKIN I2C3_ SMBA SPI2_ NSS/ I2S2_WS - - LPUART1_ RTS - - I2C3_ SCL SPI2_ SCK/ I2S2_CK - - TIM1_ CH2N - I2S2_MCK I2C3_ SDA SPI2_ MISO - TIM1_ CH3N - -
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AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_ AF TIM1/ TIM2/ LPTIM1 TIM1/ TIM2 SPI2S2 TIM1/ LPTIM3 I2C1/ I2C2/ I2C3 SPI1/ SPI2S2 RF USART1 / USART2 LPUART1 - - PC0 - LPTIM1_ IN1 - - I2C3_ SCL - - - LPUART1_ RX - PC1 - LPTIM1_ OUT - SPI2_ MOSI/ I2S2_SD I2C3_ SDA - - - LPUART1_ TX PC2 - LPTIM1_ IN2 - - - SPI2_ MISO - - PC3 - LPTIM1_ ETR - - - SPI2_ MOSI/ I2S2_SD - PC4 - - - - - - PC5 - - - - - PC6 - - - - PC13 RTC_ OUT1, RTC_TS - - PC14 -
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STM32WLE5J8/JB/JC Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies, by tests in production on 100 % of the devices, with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 5.1.6 STM32WLE5J8/JB/JC Power supply scheme Figure 11. Power supply scheme 1.55 to 3.6 V VBAT VBAT Backup circuitry (LSE, RTC and backup registers) Power switch VDD VCORE n x VDD LPR VDDIO1 Level shifter OUT GPIOs n x 100 nF + 1 x 4.7 μF IN IO logic Kernel logic (CPU, digital and memories n x VSS VDDA VDDA VREF VREF+ 10 nF + 1 μF 100 nF 1 μF ADCs COMPs VREFBUF MR VREFVSSA VDDRF VDD VDDSMPS VLXSMPS 4.
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STM32WLE5J8/JB/JC 5.1.7 Electrical characteristics Current consumption measurement Figure 12. Current consumption measurement scheme IDDSMPS VDDSMPS VDDSMPS IDDRF VDDRF VDDRF IDDVBAT VBAT VBAT VDD VDD IDD IDDA VDDA VDDA MSv64326V2 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in the tables below, may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
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Electrical characteristics STM32WLE5J8/JB/JC 2. VIN maximum must always be respected. Refer to the next table for the maximum allowed injected current values. 3. This formula must be applied only on the power supplies related to the I/O structure described in Table 19: STM32WLE5J8/JB/JC pin definition. 4. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled. 5. Include VREF- pin. Table 22.
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STM32WLE5J8/JB/JC Electrical characteristics 5.3 Operating conditions 5.3.1 Main performances Table 24. Main performances at VDD = 3 V Parameter ICORE Test conditions Core current consumption Rx boosted Tx low power Tx high power 5.3.2 Typ VBAT (VBAT = 3V, VDD = 0 V) 0.005 Shutdown 0.031 Standby (32-Kbyte RAM retention) 0.360 Stop 2, RTC enabled 1 Sleep (16 MHz) 770 LPRun (2 MHz) 220 Run, SMPS ON (48 MHz) 3450 LoRa 125 kHz, SMPS ON 4.82 434 to 490 MHz, 14 dBm, 3.
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Electrical characteristics STM32WLE5J8/JB/JC Table 25. General operating conditions (continued) Symbol Parameter PD Power dissipation at TA = 85 °C for suffix 6 version(4) TA Ambient temperature for suffix 6 version TJ Junction temperature range Conditions Min Max Unit - 392.0 mW UFBGA73 Maximum power dissipation –40 Low-power dissipation(5) Suffix 6 version 85 °C 105 –40 105 °C 1. When the reset is released, the functionality is guaranteed down to VBOR0 min. 2.
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STM32WLE5J8/JB/JC Electrical characteristics Table 26.
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Electrical characteristics STM32WLE5J8/JB/JC Table 27. Sub-GHz radio power consumption in transmit mode (SMPS ON) Symbol Frequency band (MHz) PA match (conditions) +14 dBm 868 to 915 +14 dBm (optimal settings) 434 to 490 IDD 868 to 915 434 to 490 +14 dBm Typ +14 dBm, VDDRF = 3.3 V 26 +10 dBm, VDDRF = 3.3 V 20 +14 dBm, VDDRF = 1.8 V 48 +10 dBm, VDDRF = 1.8 V 38 +15 dBm, VDDRF = 3.3 V 32.5 +10 dBm, VDDRF = 3.3 V 15 +15 dBm, VDDRF = 1.8 V 60 +10 dBm, VDDRF = 1.
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STM32WLE5J8/JB/JC Electrical characteristics Table 28.
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Electrical characteristics STM32WLE5J8/JB/JC Table 29. Sub-GHz radio receive mode specifications Symbol Description Conditions Min Typ Max BR = 0.6 Kbit/s, FDA = 0.8 kHz, BW = 4 kHz - –125 - BR = 1.2 Kbit/s, FDA = 5 kHz, BW = 20 kHz - –123 - - –117 - - –108 - BR = 250 Kbit/s, FDA = 125 kHz, BW = 500 kHz - –103 - BW = 10.4 kHz, SF = 7 - –135 - BW = 10.
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STM32WLE5J8/JB/JC Electrical characteristics Table 29. Sub-GHz radio receive mode specifications (continued) Symbol BI_L IIP3 IMA Description Conditions Blocking immunity, LoRa Third order input intercept point Image attenuation Min Typ Max Unit Offset = ±1 MHz, BW = 125 kHz, SF = 12 - 87 - Offset = ±2 MHz, BW = 125 kHz, SF = 12 - 91 - Offset = ±10 MHz, BW = 125 kHz, SF = 12 - 96 - Unwanted tones are 1 MHz and 1.96 MHz above LO.
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Electrical characteristics STM32WLE5J8/JB/JC Table 30. Sub-GHz radio transmit mode specifications (continued) Symbol Description Conditions TXRMP PA ramping time Programmable TS_TX TX wakeup time Frequency synthesizer enabled Min Typ Max 10 - 3400 - 36 + PA ramping - Unit µs 1. For low-power PA, +15 dBm maximum RF output power can be reached with optimal settings. Table 31.
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STM32WLE5J8/JB/JC Electrical characteristics Table 31. Sub-GHz radio power management specifications (continued) Symbol Description Frequency (MHz) Conditions Unit 470 490 868 VDD = 3.3 V, ILOAD = 0 to 100 mA, current limiter off - 95 - VDD = 3.3 V, ILOAD = 100 mA, current limiter on - 380 - VDD = 3.
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Electrical characteristics STM32WLE5J8/JB/JC Table 33.
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STM32WLE5J8/JB/JC Electrical characteristics 1. Continuous mode means Run and Sleep modes, or temperature sensor enable in LPRun and LPSleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except Shutdown) and its consumption is therefore included in the supply current characteristics tables. 5.3.
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Electrical characteristics STM32WLE5J8/JB/JC Figure 13. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V2 5.3.
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Conditions Symbol Parameter - Voltage scaling Range 2 SMPS Range 2 IDD(Run) Supply current in Run mode DS13105 Rev 4 fHCLK = fMSI All peripherals disabled Range 1 SMPS Range 1 IDD (LPRun) Supply current fHCLK = fMSI in LPRun mode All peripherals disabled Unit fHCLK (MHz) 25 °C 55 °C 85 °C 25 °C 85 °C 16 1.85 1.90 1.95 2.20 2.40 8 1.10 1.15 1.20 1.40 1.60 2 0.585 0.610 0.670 TBD TBD 16 1.60 1.60 1.65 TBD TBD 8 1.00 1.05 1.05 TBD TBD 2 0.730 0.750 0.
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Conditions Symbol Parameter - Voltage scaling Range 2 SMPS Range 2 IDD(Run) Supply current in Run mode fHCLK = fMSI All peripherals disabled DS13105 Rev 4 Range 1 SMPS Range 1 IDD(LPRun) Supply current fHCLK = fMSI in LPRun mode All peripherals disabled Max(1) Typ Unit fHCLK (MHz) 25 °C 55 °C 85 °C 25 °C 85 °C 16 1.90 1.90 2.00 2.20 2.40 8 1.10 1.15 1.20 1.40 1.60 2 TBD TBD TBD TBD TBD 16 1.45 1.45 1.50 TBD TBD 8 1.00 1.05 1.05 TBD TBD 2 0.730 0.750 0.
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Conditions Symbol Typ Parameter - Voltage scaling Code 1.90 118.75 1.85 115.63 Dhrystone 2.1 1.85 115.63 Fibonacci 1.80 112.50 While(1) 1.60 100.00 1.45 90.63 1.40 87.50 Dhrystone 2.1 1.40 87.50 Fibonacci 1.40 87.50 While(1) 1.30 Reduced code 5.70 CoreMark(1) 5.55 115.63 Dhrystone 2.1 5.50 114.58 Fibonacci 5.40 112.50 While(1) 4.65 96.88 Reduced code 3.50 72.92 CoreMark(1) 3.40 70.83 Dhrystone 2.1 3.40 70.83 Fibonacci 3.30 68.75 While(1) 2.90 60.
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Conditions Symbol Typ Unit - IDD(LPRun) Typ Parameter Voltage scaling Supply current in fHCLK = fMSI = 2 MHz LPRun mode All peripherals disabled Code Unit 25 °C 25 °C Reduced code 0.225 112.50 CoreMark(1) 0.220 110.00 Dhrystone 2.1 0.220 Fibonacci 0.240 120.00 While(1) 0.175 87.50 µA 110.00 µA/MHz Electrical characteristics 76/135 Table 37.
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Conditions Symbol Typ Parameter - Voltage scaling Code 1.95 121.88 CoreMark 1.90 118.75 Dhrystone 2.1 1.90 118.75 Fibonacci 1.90 118.75 While(1) 1.75 109.38 1.45 90.63 CoreMark 1.45 90.63 Dhrystone 2.1 1.45 90.63 Fibonacci 1.45 90.63 While(1) 1.35 Reduced code 5.90 CoreMark(1) 5.65 117.71 Dhrystone 2.1 5.70 118.75 Fibonacci 5.65 117.71 While(1) 5.10 106.25 Reduced code 3.60 75.00 CoreMark(1) 3.45 71.88 Dhrystone 2.1 3.50 72.92 Fibonacci 3.45 71.
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Conditions Symbol Typ Parameter - (2) IDD(LPRun) Typ Unit Voltage scaling Supply current fHCLK = fMSI = 2 MHz in LPRun mode All peripherals disabled Code Unit 25 °C 25 °C Reduced code 0.225 112.50 CoreMark(1) 0.220 110.00 Dhrystone 2.1 0.225 Fibonacci 0.225 112.50 While(1) 0.195 97.50 µA 112.50 µA/MHz Electrical characteristics 78/135 Table 38. Typical current consumption in Run and LPRun modes, with different codes running from SRAM1 (continued) 1.
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Conditions Symbol Parameter - Voltage scaling Range 2 IDD(Sleep) Supply current in fHCLK = fMSI Sleep mode All peripherals disabled Range 1 DS13105 Rev 4 SMPS Range 1 IDD(LPSleep) Supply current in fHCLK = fMSI LPSleep mode All peripherals disabled Max(1) Typ Unit fHCLK (MHz) 25 °C 55 °C 85 °C 25 °C 85 °C 16 0.770 0.800 0.860 1.00 1.30 8 0.570 0.600 0.655 0.780 0.990 2 0.445 0.470 0.525 0.650 0.860 48 1.70 1.70 1.80 2.10 2.30 32 1.25 1.30 1.40 1.60 1.
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Conditions Symbol Max(1) Typ Parameter Unit - IDD(LPSleep) Electrical characteristics 80/135 Table 40. Current consumption in LPSleep mode, Flash memory in power-down Supply current in LPSleep mode fHCLK (MHz) 25 °C 55 °C 85 °C 25 °C 85 °C 2 58.0 74.5 125 86.0 330 1 35.5 50.5 99.0 60.0 300 0.4 18.5 33.5 81.5 41.0 280 0.1 11.0 26.5 74.5 36.0 280 fHCLK = fMS All peripherals disabled µA 1. Guaranteed by characterization results, unless otherwise specified. Table 41.
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Symbol IDD(Stop 1) IDD (Stop 1with RTC) Conditions Parameter Supply current in Stop 1 mode RTC disabled Supply current in Stop 1 mode RTC enabled, clocked by LSI(2) Max(1) Typ VDD (V) 0 °C 25 °C 55 °C 85 °C 0 °C 25 °C 85 °C 1.8 2.05 4.00 14.0 47.0 6.10 20.0 200 2.4 2.15 3.95 14.0 47.0 TBD TBD TBD 3.0 2.15 4.15 14.0 47.5 5.90 20.0 200 3.6 2.25 4.20 14.0 48.0 6.20 20.0 200 1.8 2.30 4.35 14.0 47.0 6.30 20.0 200 2.4 2.50 4.35 14.5 47.
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Symbol Parameter Conditions - No retention IDD (Standby) Supply current in Standby mode RTC disabled Backup registers retained SRAM2 retained DS13105 Rev 4 RTC clocked by LSI (PREDIV = 1) Supply current in Standby mode IDD (backup registers and SRAM2 (Standby with retained) RTC) RTC enabled RTC clocked by LSE quartz(2) in low drive mode Max(1) Typ VDD (V) 0 °C 25 °C 55 °C 85 °C 0 °C 25 °C 85 °C 1.8 0.009 0.027 0.245 1.00 TBD TBD TBD 2.4 0.022 0.051 0.340 1.35 TBD TBD TBD 3.
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Symbol IDD (Shutdown) Parameter Conditions - VDD (V) 0 °C 25 °C 55 °C 85 °C 0 °C 25 °C 85 °C 1.8 0.001 0.008 0.105 0.380 0.001 0.043 1.70 2.4 0.008 0.018 0.135 0.445 TBD TBD TBD 3.0 0.018 0.031 0.180 0.545 0.078 0.150 2.40 3.6 0.041 0.062 0.260 0.690 0.110 0.190 2.90 1.8 0.054 0.065 0.145 0.545 TBD TBD TBD 2.4 0.090 0.105 0.200 0.665 TBD TBD TBD 3.0 0.160 0.175 0.295 0.860 TBD TBD TBD 3.6 0.250 0.280 0.440 1.15 TBD TBD TBD 1.8 0.
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Symbol Conditions Parameter - RTC disabled IDD(VBAT) Backup domain supply current RTC enabled and clocked by LSE quartz(1) Typ VBAT (V) 0 °C 25 °C 55 °C 85 °C 1.8 1.00 3.00 19.0 95.0 2.4 1.00 3.00 22.0 110 3.0 1.00 5.00 31.0 150 3.6 3.00 11.0 50.0 220 1.8 140 150 180 275 2.4 155 170 200 310 3.0 185 200 235 375 3.6 230 245 295 485 Unit nA Electrical characteristics 84/135 Table 46. Current consumption in VBAT mode 1.
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STM32WLE5J8/JB/JC Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: a static and a dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 67: I/O static characteristics.
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Electrical characteristics STM32WLE5J8/JB/JC On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the table below. The device is placed under the following conditions: • All I/O pins are in analog mode.
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STM32WLE5J8/JB/JC Electrical characteristics Table 48. Peripheral current consumption (continued) Peripheral APB1 Range 1 Range 2 LPRun and LPSleep I2C3 independent clock domain 2.29 1.88 1.30 LPTIM1 1.67 1.44 1.50 LPTIM1 independent clock domain 2.50 2.19 1.45 LPTIM2 1.67 1.38 0.900 LPTIM2 independent clock domain 2.50 2.13 1.55 LPTIM3 0.833 0.688 0.650 LPTIM3 independent clock domain 2.29 1.94 0.650 LPUART1 20.8 1.81 3.55 LPUART1 independent clock domain 2.50 2.
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Electrical characteristics STM32WLE5J8/JB/JC Table 49. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Wakeup time from Sleep to Run mode Wakeup time from tWULPSLEEP LPSleep to LPRun mode tWUSTOP0 Conditions Wakeup time from Stop 0 mode in Flash memory(2) - tWUSTOP1 4.38 Wakeup clock MSI = 48 MHz 2.14 2.90 Wakeup clock MSI = 16 MHz 2.78 3.58 Wakeup clock HSI16 = 16 MHz 1.99 TBD Wakeup clock HSI16 = 16 MHz with HSIKERON enabled 1.01 1.13 Wakeup clock MSI = 4 MHz 6.79 8.
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STM32WLE5J8/JB/JC Electrical characteristics Table 50. Regulator modes transition times(1) Symbol Parameter Conditions tWULPRUN Wakeup time from LPRun to Run mode(2) tVOST Regulator transition time from Range 2 to Range 1(3) Regulator transition time from Range 1 to Range 2(3) Code run with MSI = 2 MHz Typ Max 19.6 TBD 21.9 32.2 23.1 33.9 Unit µs Code run with HSI16 1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C). 2. Time until REGLPF flag is cleared in PWR_SR2. 3.
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Electrical characteristics STM32WLE5J8/JB/JC Table 52. HSE32 oscillator characteristics (continued) Symbol Parameter Conditions HSEGMC = 000, SUBGHZ_HSEINTRIMR = 0x12 IDDRF(HSE) HSE32 current consumption XOTg(HSE) SUBGHZ_HSEINTRIMR granularity SUBGHZ_HSEINTRIMR number of tuning bits XOTst(HSE) SUBGHZ_HSEINTRIMR setting time Typ Max Unit - 50 - µA - 1 5 ppm SUBGHZ_HSEINTRIMR XOTfp(HSE) frequency pulling XOTnb(HSE) Min ±15 ±30 - - 6 - bit - - 0.
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STM32WLE5J8/JB/JC Electrical characteristics the resonator and the load capacitors have to be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 54.
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Electrical characteristics STM32WLE5J8/JB/JC Figure 15. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% VLSEL 10% tr(LSE) t tf(LSE) tw(LSEL) TLSE MS19215V2 Table 55. Low-speed external user clock characteristics(1) – Bypass mode Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - 21.2 32.768 44.4 VLSEH OSC32_IN input pin highlevel voltage - 0.
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STM32WLE5J8/JB/JC Electrical characteristics Table 56. HSI16 oscillator characteristics(1) (continued) Symbol Parameter TRIM HSI16 user trimming step DuCy(HSI16) (2) Conditions Min Typ Max Trimming code is not a multiple of 48 0.2 0.3 0.4 Trimming code is a multiple of 48 –4 –6 –8 45 - 55 TA = 0 to 85 °C –1 - 1 TA = -40 to 125 °C –2 - 1.5 –0.1 - 0.
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Electrical characteristics STM32WLE5J8/JB/JC Multi-speed internal (MSI) RC oscillator Table 57. MSI oscillator characteristics(1) Symbol Parameter Conditions MSI mode fMSI ∆TEMP(MSI)(2) 94/135 MSI frequency after factory calibration, done at VDD= 3 V and TA= 30 °C MSI oscillator frequency drift over temperature Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 789.6 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.
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STM32WLE5J8/JB/JC Electrical characteristics Table 57. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD = 1.8 to 3.6 V –1.2 - VDD = 2.4 to 3.6 V –0.5 - VDD = 1.8 to 3.6 V –2.5 - VDD = 2.4 to 3.6 V –0.8 - VDD = 1.8 to 3.6 V –5 - VDD = 2.4 to 3.6 V –1.
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Electrical characteristics STM32WLE5J8/JB/JC Table 57. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(4) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 1.
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STM32WLE5J8/JB/JC Electrical characteristics Figure 17. Typical current consumption vs. MSI frequency Low-speed internal (LSI) RC oscillator Table 58. LSI oscillator characteristics(1) Symbol fLSI Parameter LSI frequency tSU(LSI)(2) (2) tSTAB(LSI) IDD(LSI)(2) Conditions Min Typ Max VDD = 3 V, TA = 30 °C 31.04 - 32.96 VDD = 1.8 to 3.6 V, TA = -40 to 125 °C 29.
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Electrical characteristics 5.3.11 STM32WLE5J8/JB/JC PLL characteristics Parameters given in the table below are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 25: General operating conditions. Table 59. PLL characteristics(1) Symbol fPLL_IN Parameter Conditions Min Typ Max Unit PLL input clock(2) - 2.
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STM32WLE5J8/JB/JC Electrical characteristics Table 60. Flash memory characteristics(1) (continued) Symbol Parameter Conditions Average consumption from VDD IDD Maximum current (peak) Typ Max Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 6 µs) - Erase mode 7 (for 67 µs) - Unit mA 1. Guaranteed by design. Table 61.
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Electrical characteristics STM32WLE5J8/JB/JC Table 62. EMS characteristics Symbol Parameter Conditions Level/Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 48 MHz, conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
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STM32WLE5J8/JB/JC Electrical characteristics Table 63. EMI characteristics Symbol Parameter Monitored frequency band Conditions Peripheral ON SMPS OFF fHSE = /fCPUM4, fCPUM0] Unit fHSE = 32 MHz fCPU = 48 MHz SEMI 5.3.14 Peak level VDD = 3.6 V, TA = 25 °C, UFBGA73 package compliant with IEC 61967-2 0.
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Electrical characteristics 5.3.15 STM32WLE5J8/JB/JC I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3V-capable I/O pins), must be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in case abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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STM32WLE5J8/JB/JC Electrical characteristics Table 67. I/O static characteristics Symbol Parameter Conditions I/O input low-level voltage(1) VIL Vhys Typ Max - - 0.3 x VDD 0.7 x VDD - - 0.49 x VDD + 0.26 - - - 200 - 0 ≤ VIN ≤ Max(VDDXXX)(3) - - ±100 Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX) +1 V(2)(3)(4) - - 650 Max(VDDXXX) +1 V < VIN ≤ 5.
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Electrical characteristics STM32WLE5J8/JB/JC All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in the figure below. Figure 18.
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STM32WLE5J8/JB/JC Electrical characteristics Table 68. Output voltage characteristics(1) Symbol Parameter Conditions VOL(2) Output low-level voltage for an I/O pin Min Max - 0.4 VDD - 0.4 - - 0.4 2.4 - - 1.3 VDD - 1.3 - - 0.4 VDD - 0.45 - |IIO| = 20 mA, VDD ≥ 2.7 V - 0.4 |IIO| = 10 mA, VDD ≥ 1.8 V - 0.4 |IIO| = 2 mA, 1.8 V ≥ VDD ≥ 1.08 V - 0.4 VOH(2) CMOS port(3) |I Output high-level voltage for an I/O pin IO| = 8 mA, VDD ≥ 2.
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Electrical characteristics STM32WLE5J8/JB/JC Table 69. I/O AC characteristics(1)(2) (continued) OSPEEDx[1:0](3) Symbol Fmax Parameter Conditions Maximum frequency 0b01 Tr/Tf Fmax Output rise and fall time Maximum frequency 0b10 Tr/Tf Fmax Output rise and fall time Maximum frequency 0b11 Tr/Tf Output rise and fall time Min Max C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25 C = 50 pF, 1.8 V ≤ VDD ≤ 2.7 V - 10 C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50 C = 10 pF, 1.8 V ≤ VDD ≤ 2.
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STM32WLE5J8/JB/JC Electrical characteristics Table 70. NRST pin characteristics(1) Symbol Conditions Min Typ Max VIL(NRST) NRST input low level voltage - - - 0.3 x VDD VIH(NRST) NRST input high level voltage - 0.7 x VDD - - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN = VSS 25 40 55 kΩ - - - 70 1.8 V ≤ VDD ≤ 3.
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Electrical characteristics 5.3.19 STM32WLE5J8/JB/JC Analog-to-digital converter characteristics Unless otherwise specified, the parameters given in the table below are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 25: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 72.
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STM32WLE5J8/JB/JC Electrical characteristics Table 72. ADC characteristics(1) (continued) Symbol tLATR ts Parameter Trigger conversion latency; Regular and injected channels without conversion abort Sampling time Conditions(2) Min Typ Max CKMODE = 00 2 - 3 CKMODE = 01 - - 2.75 CKMODE = 10 - - 2.63 CKMODE = 11 - - 3 fADC = 35 MHz 0.043 - 4.59 µs - 1.5 - 160.5 1/fADC - - - 20 µs 0.40 - 4.
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Electrical characteristics STM32WLE5J8/JB/JC Table 73. Maximum ADC RAIN values (continued) Resolution Sampling cycle at 35 MHz (ns) Sampling time at 35 MHz (ns) Max. RAIN(1)(2)(Ω) 1.5(3) 43 68 3.5 100 820 7.5 214 3300 12.5 357 5600 19.5 557 10000 39.5 1129 22000 79.5 2271 39000 160.5 4586 50000 43 82 3.5 100 1500 7.5 214 3900 12.5 357 6800 19.5 557 12000 39.5 1129 27000 79.5 2271 50000 160.5 4586 50000 43 390 3.5 100 2200 7.5 214 5600 12.
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STM32WLE5J8/JB/JC Electrical characteristics Table 74. ADC accuracy(1)(2)(3) Symbol ET EO EG ED EL ENOB Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Effective number of bits Conditions(4) Min Typ Max VDDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C - 3 4 2 V < VDDA = VREF+ < 3.6 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range - 3 6.5 1.65 V < VDDA = VREF+ < 3.
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Electrical characteristics STM32WLE5J8/JB/JC Table 74. ADC accuracy(1)(2)(3) (continued) Symbol Parameter Conditions(4) Min Typ Max 62.5 63 - 59.5 63 - 59 63 - 63 64 - 60 64 - 60 64 - VDDA = VREF+ = 3 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C - -74 -73 2 V < VDDA = VREF+ < 3.6 V, fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range - -74 -70 1.65 V < VDDA = VREF+ < 3.6 V, TA = entire range, Range 1: fADC = 35 MHz, fs ≤ 2.2 Msps Range 2: fADC = 16 MHz, fs ≤ 1.
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STM32WLE5J8/JB/JC Electrical characteristics Figure 20. ADC accuracy characteristics EG Code (1) Example of an actual transfer curve 4095 (2) Ideal transfer curve 4094 (3) End point correlation line 4093 ET total unadjusted error: maximum deviation between the actual and ideal transfer curves. (2) ET (3) 7 (1) 6 EO offset error: maximum deviation between the first actual transition and the first ideal one. EG gain error: deviation between the last ideal transition and the last actual one.
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Electrical characteristics 5.3.20 STM32WLE5J8/JB/JC Temperature sensor characteristics Table 75. TS characteristics Symbol Parameter TL(1) VTS linearity with temperature (2) Avg_Slope Average slope Voltage at 30 °C (±5 °C)(3) V30 Min Typ Max Unit - ±1 ±2 °C 2.3 2.5 2.7 mV / °C 0.742 0.76 0.
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STM32WLE5J8/JB/JC 5.3.22 Electrical characteristics Voltage reference buffer characteristics Table 78. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode(2) Normal mode VREFBUF_ OUT Voltage reference output Degraded mode(2) Min Typ Max VRS = 0 2.4 - 3.6 VRS = 1 2.8 - 3.6 VRS = 0 1.65 - 2.4 VRS = 1 1.65 - 2.8 2.048 2.049(3) (3) VRS = 0 2.046 VRS = 1 2.498(3) 2.5 2.
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Electrical characteristics STM32WLE5J8/JB/JC Table 78. VREFBUF characteristics(1) (continued) Symbol Parameter VREFBUF IDDA consumption (VREFBUF) from VDDA Conditions Min Typ Max Iload = 0 µA - 16 25 Iload = 500 µA - 18 30 Iload = 4 mA - 35 50 Unit µA 1. Guaranteed by design, unless otherwise specified. 2. In degraded mode, VREFBUF cannot maintain accurately the output voltage that follows (VDDA - drop voltage). 3. Guaranteed by test in production. 4.
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STM32WLE5J8/JB/JC Electrical characteristics Table 79. DAC characteristics(1) (continued) Symbol Parameter Conditions ±0.5 LSB Normal mode Settling time (full scale: for ±1 LSB DAC output a 12-bit code transition ±2 LSB between the lowest and the buffer ON tSETTLING highest input codes, when CL ≤ 50 pF ±4 LSB RL ≥ 5 kΩ DAC_OUT reaches final ±8 LSB value ±0.5 LSB, ±1 LSB, ±2 LSB, ±4 LSB, ±8 LSB) Normal mode DAC output buffer OFF, ±1LSB, CL = 10 pF Min Typ Max - 1.7 3 - 1.6 2.9 - 1.55 2.
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Electrical characteristics STM32WLE5J8/JB/JC Table 79. DAC characteristics(1) (continued) Symbol Parameter Conditions DAC output buffer ON DAC consumption from IDDA(DAC) VDDA DAC output buffer OFF Min Typ Max No load, middle code (0x800) - 315 500 No load, worst code (0xF1C) - 450 670 No load, middle code (0x800) - - 0.
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STM32WLE5J8/JB/JC Electrical characteristics Table 80. DAC accuracy(1) .
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Electrical characteristics STM32WLE5J8/JB/JC Table 80. DAC accuracy(1) (continued) Symbol ENOB Parameter Effective number of bits Conditions Min Typ Max DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.4 - DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - Unit bits 11.5 - 1. Guaranteed by design. 2. Difference between two consecutive codes - 1 LSB. 3. Difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095. 4.
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STM32WLE5J8/JB/JC Electrical characteristics Table 81. COMP characteristics(1) (continued) Symbol Parameter Conditions Ultra-lowpower mode IDDA(COMP) Comparator consumption from VDDA Medium mode High-speed mode Min Typ Max Static - 400 600 With 50 kHz ±100 mV overdrive square signal - 1200 - Static - 5 7 With 50 kHz ±100 mV overdrive square signal - 6 - Static - 70 100 With 50 kHz ±100 mV overdrive square signal - 75 - Unit nA µA 1.
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Electrical characteristics STM32WLE5J8/JB/JC Table 83. IWDG min/max timeout period at 32 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout (RL[11:0] = 0x000) Max timeout (RL[11:0] = 0xFFF) /4 0x0 0.125 512 /8 0x1 0.250 1024 /16 0x2 0.500 2048 /32 0x3 1.0 4096 /64 0x4 2.0 8192 /128 0x5 4.0 16384 /256 0x6 or 0x7 8.0 32768 Unit ms 1.
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STM32WLE5J8/JB/JC Electrical characteristics All I2C SDA and SCL I/Os embed an analog filter (refer to the table below for its characteristics). Table 85. I2C analog filter characteristics(1) Symbol tAF Parameter Min (2) Maximum pulse width of spikes that are suppressed by the analog filter 50 Max 100 (3) Unit ns 1. Guaranteed by characterization. 2. Spikes with widths below tAF(min) filtered. 3. Spikes with widths above tAF(max) not filtered.
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Electrical characteristics STM32WLE5J8/JB/JC SPI characteristics Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 25: General operating conditions, with the following configuration: • output speed set to OSPEEDRy[1:0] = 11 • capacitive load C = 30 pF • measurements done at CMOS levels: 0.5 x VDD Refer to Section 5.3.
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STM32WLE5J8/JB/JC Electrical characteristics Table 87. SPI characteristics(1) (continued) Symbol tv(SO) Parameter Data output valid time tv(MO) th(SO) th(MO) Data output hold time Conditions Min Typ Max Slave mode, 2.7 < VDD < 3.6 V Range 1 - 10 13.5 Slave mode, 2.7 < VDD < 3.6 V Range 2 - 17 18 Slave mode, 1.8 < VDD < 3.6 V Range 1 - 10 20 Slave mode, 1.8 < VDD < 3.6 V Range 2 - 17 24 Master mode (after enable edge) - 1 1.
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Electrical characteristics STM32WLE5J8/JB/JC Figure 24. SPI timing diagram - Slave mode and CPHA = 1 NSS input SCK input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 th(NSS) tc(SCK) tw(SCKH) tw(SCKL) th(SO) tv(SO) ta(SO) MISO OUTPUT MSB OUT tdis(SO) LSB OUT th(SI) tsu(SI) MOSI INPUT BIT6 OUT tr(SCK) tf(SCK) MSB IN BIT 1 IN LSB IN ai14135b 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 25.
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STM32WLE5J8/JB/JC Electrical characteristics JTAG/SWD characteristics Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 25: General operating conditions, with the following configuration: • capacitive load C = 30 pF • measurement done at CMOS levels: 0.5 x VDD. Refer to Section 5.3.16: I/O port characteristics for more details. Table 88.
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Package information 6 STM32WLE5J8/JB/JC Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. 6.1 UFBGA73 package information Figure 26.
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STM32WLE5J8/JB/JC Package information Table 90. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A(2) - - 0.60 - - 0.236 A1 - - 0.11 - - 0.0043 A2 - 0.13 - - 0.0051 - A4 - 0.32 - - 0.0126 - (3) 0.24 0.29 0.34 0.0094 0.0114 0.0134 D 4.85 5.00 5.15 0.1909 0.1969 0.2028 D1 - 4.00 - - 0.1575 - E 4.85 5.00 5.15 0.1909 0.1969 0.2028 E1 - 4.00 - - 0.
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Package information STM32WLE5J8/JB/JC Figure 27. UFBGA - 73 balls, 5 × 5 mm, ultra thin fine pitch ball grid array recommended footprint Dpad Dsm MSv62396V1 Table 91. UFBGA recommended PCB design rules (0.5 mm pitch BGA) Dimension 130/135 Recommended values Pitch 0.5 mm Dpad 0.230 mm Dsm 0.330 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm Ball diameter 0.
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STM32WLE5J8/JB/JC Package information Device marking for UFBGA73 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 28. UFBGA73 marking example (package top view) Product identification(1) WLE5J8I6 Date code Y WW R Revision code Pin 1 identifier MSv64357V1 1.
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Package information STM32WLE5J8/JB/JC As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the device power consumption. RF characteristics (such as sensitivity, Tx power consumption) are provided up to 85 °C. Table 92. Package thermal characteristics Symbol ΘJA ΘJB Parameter Unit 20.1 Thermal resistance junction-ambient UFBGA73 - 5 mm x 5 mm ΘJC 132/135 Value 20.2 31.
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STM32WLE5J8/JB/JC 7 Ordering information Ordering information Example: STM32 WL E5 J 8 I 6 TR Device family STM32 = Arm® based 32-bit microcontroller Product type WL = wireless long range Device subfamily E5 = Cortex-M4, full set of modulations Pin count J = 73 pins Flash memory size 8 = 64 Kbytes B = 128 Kbytes C = 256 Kbytes Package I = UFBGA (5 x 5mm) Temperature range 6 = Industrial temperature range, -40 to 85 °C (105 °C junction) Packing TR = tape and reel xxx = programmed parts For a list
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Revision history 8 STM32WLE5J8/JB/JC Revision history Table 93. Document revision history Date Revision 20-Dec-2019 1 Initial release. 8-Jan-2020 2 Updated Ultra-low-power platform features. 25-Feb-2020 3 Updated: – TJ in Table 2: Main features and peripheral counts and in the whole doc – Section 3.9.
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STM32WLE5J8/JB/JC IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.