Datasheet

Note:

1.Thisiscurrentcapabilityperpowerpin.

2.ThesepinsareconnectedtoNVIDIA®Tegra®directly.Theyareopen-drain(eitherpulledupordrivenlowbyTegrawhen

conﬁguredasoutputs).ThemaxdrivethatmeetsthedatasheetVOLis1mA.

3.ThesepinsconnecttoTITXB0108leveltranslators.Duetothedesignofthesedevices, theoutputdriversareveryweak,so

theycanbeoverdrivenbyanotherconnecteddeviceoutputforbidirectionalsupport.

4.IntheType/Dircolumn,outputistoexpansionheader.Inputisfromexpansionheader.Bidirisforbidirectionalsignals.

Wheretwodirectionsareshown,theﬁrstisfortheprimaryfunction(mostlyGPIOs)andthesecondisforthealternate

function.

5.WherethesignaldirectionisinputoroutputinTable3-3,thismatchesthetypicalspecialfunctionusage(e.g.SPI,I2S,etc.).

Thedirectionisbidirectionaliftheseare conﬁguredasGPIOs.

6.Allsignalsonthe40-pinheaderare3.3Vlevels.