Datasheet
40-Pin Expansion Header - J10
40-Pin part 1
13
– – – Main3.3VSupply –
– – – Main5.0VSupply –
I2C1_SDA 191 GEN2_I2C_SDA I2C#1Data GPIO
– – – Main5.0VSupply –
I2C1_SCL 189 GEN2_I2C_SCL I2C#1Clock GPIO
– – – Ground –
GPIO09 211 AUD_MCLK GPIO AudioMasterClock
UART1_TXD 203 UART2_TXD UART#1Transmit GPIO
– – – Ground –
UART1_RXD 205 UART2_RXD UART#1Receive GPIO
UART1_RTS* 207 UART2_RTS GPIO UART#2RequesttoSend
I2S0_SCLK 199 DAP4_SCLK GPIO AudioI2S#0Clock
SPI1_SCK 106 SPI2_SCK GPIO SPI#
1ShiftClock
– – – Ground –
GPIO12 218 LCD_TE GPIO –
SPI1_CSI1* 112 SPI2_CS1 GPIO SPI#1ChipSelect#1
– – – Main3.3VSupply –
SPI1_CSI0* 110 SPI2_CS0 GPIO SPI#0ChipSelect#0
SPI0_MOSI 89 SPI1_MOSI GPIO SPI#0MasterOut/SlaveIn
– – – Ground –
SPI0_MISO 93 SPI1_MISO GPIO SPI#0MasterIn/SlaveOut
SPI1_MISO 108 SPI2_MISO GPIO SPI#1MasterIn/Slave Out
SPI0_SCK 91 SPI1_SCK GPIO SPI#0ShiftClock
SPI0_CS0* 95 SPI1_CS0 GPIO SPI#0ChipSelect#0
– – – Ground –
SPI0_CS1* 97 SPI1_CS1 GPIO SPI#0ChipSelect#1
I2C0_SDA 187 GEN1_I2C_SDA I2C#0Data
HeaderPin# Module PinName ModulePin# Tegra Pinname Default Usage /Description AlternateFunctionality
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GPIO
I2C0_SCL 185 GEN1_I2C_SCL I2C#0Clock GPIO
GPIO01 118 CAM_AF_EN GPIO CameraMCLK#2
– – – Ground –
GPIO11 216 GPIO_PZ0 GPIO CameraMCLK#3
GPIO07 206 LCD_B
L_PWM GPIO PWM
GPIO13 228 GPIO_PE6 GPIO PWM
– – – Ground –
I2S0_FS 197 DAP4_FS GPIO AudioI2S#0FieldSelect
UART1_CTS* 209 UART2_CTS GPIO UART#1Clear toSend
SPI1_MOSI 104 SPI2_MOSI GPIO SPI#1MasterOut/SlaveIn
I2S0_DIN 195 DAP4_DIN GPIO AudioI2S#0Datain
– – – Ground –
I2S0_DOUT 193 DAP4_DOUT GPIO AudioI2S#0Data Out