Datasheet
SH1107
9
Functional Description
Microprocessor Interface Selection
The 8080-Parallel Interface, 6800-Parallel Interface, Serial Interface (SPI) or I
2
C Interface can be selected by different
selections of IM0~2 as shown in Table 1.
Table 1
Config Data signal Control signal
Interface
IM0
IM1
IM2
D7
D6
D5
D4
D3
D2
D1
D0
E/
RD
WR
CS
A0
RES
6800
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
E
WR/
CS
A0
RES
8080
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
RD
WR
CS
A0
RES
4-Wire SPI
0
0
0
Hz(Note1)
SI SCL
Pull High or
Low
CS
A0
RES
3-Wire SPI
1
0
0
Hz(Note1)
SI SCL
Pull High or
Low
CS
Pull
Low
RES
I
2
C
0
1
0
Hz(Note1)
SDA
SCL
Pull High or
Low
Pull
Low
SA0
RES
Note1: When Serial Interface (SPI) or I
2
C Interface is selected, D7~D2 is Hz. D7~D2 is recommended to connect the VDD or
VSS. It is also allowed to leave D7~D2 unconnected.
6800-series Parallel Interface
The parallel interface consists of 8 bi-directional data pads (D7-D0), WR (
W/R
),
RD
(E), A0 and
CS
. When
WR
(
W/R
) =
“H”, read operation from the display RAM or the status register occurs. When
WR
(
W/R
) = “L”, Write operation to display data
RAM or internal command registers occurs, depending on the status of A0 input. The
RD
(E) input serves as data latch signal
(clock) when it is “H”, provided that
CS
= “L” as shown in Table 2.
Table 2
IM0
IM1
IM2
Type
CS
A0
RD
WR
D0 to D7
0 0 1 6800 microprocessor bus
CS
A0 E
WR /
D0 to D7
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing are
internally performed, which require the insertion of a dummy read before the first actual display data read. This is shown in
Figure 2 below.