Datasheet

SH1107
23
Commands
The SH1107 uses a combination of A0,
RD
(E) and
WR
(
W/R
) signals to identify data bus signals. As the chip analyzes and
executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its
busy check is usually not required. The 8080 series microprocessor interface enters a read status when a low pulse is input to
the
RD
pad and a write status when a low pulse is input to the
WR
pad. The 6800 series microprocessor interface enters a
read status when a high pulse is input to the
W/R
pad and a write status when a low pulse is input to this pad. When a high
pulse is input to the E pad, the command is activated. (For timing, see AC Characteristics.). Accordingly, in the command
explanation and command table,
RD
(E) becomes 1(HIGH) when the 6800 series microprocessor interface reads status of
display data. This is an only different point from the 8080 series microprocessor interface.
Taking the 8080 series, microprocessor interface as an example command will explain below. When the serial interface is
selected, input data starting from D7 in sequence.
Command Set
1. Set Lower Column Address: (00H - 0FH)
2. Set Higher Column Address: (10H - 17H)
Specify column address of display RAM. Divide the column address into 4 higher bits and 4 lower bits. Set each of them into
successions. When the microprocessor repeats to access to the display RAM, the column address counter is incremented
during each access until address 127 is accessed (In page addressing mode).The page address is not changed during this
time.
A6 A5 A4 A3 A2 A1 A0 Display address
0 0 0 0 0 0 0 0(POR)
0 0 0 0 0 0 1 1
: :
1 1 1 1 1 1 1 127
Note: Don’t use any commands not mentioned above.
A0
RD
(E)
WR
(
WR /
)
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 0 1 0 A6 A5 A4
0 1 0 0 0 0 0 A3 A2 A1 A0
High bits
Low bits