Datasheet

SH1107
2
Block Diagram
Segment
driver
Common
driver
Segment
driver
Display data latch
128*128 -dots
Display Data RAM
Column address decoder
7-bit column address counter
7-bit column address counter
Display timing
generator circuit
OscillatorBus HoderCommand DecoderBus Hoder
Microprocessor Interface I/O Buffer
Page Address
Register
Output status
selecor circuit
DC-DC
Power supply
circuit
AVDD
A0
(SA0)(E)
IM0IM1IM2
SEG0 SEG2...SEG126 COM0 ...COM127 SEG127... SEG3 SEG1
Shift
register
CL
CLS
D7 D6 D5 D4 D3 D2 D1 D0
(SI/SDA) (SCL)
SW
FB
VBREF
VCOMH
VCL
VSL
IREF
Vpp
VDD
VSS
I/O buffer circuit
line address decoder
Line counter
Initial display line register
SENSE
CS RD
WR
RES
(R/W)
FRM
Figure 1 SH1107 Block Diagram