Datasheet
SH1107
16
S
0 1 1 1 1 0
S
A
0
1 A
data byte
A
data byte
A
data byte
A
data byte
A P
slave address
READ
A
1 DC control byte
A
data byte
A
0 DC control byte
A
data byte
S 0 1 1 1 1 0
S
A
0
0 A P
2n>=0 bytes 1 byte
n>=0 bytes
MSB.................LSB
slave address
C
0
WRITE
R
W
0 1 1 1 1 0
S
A
0
A
C
0
DC 0 0 0 0 0 0
slave address
Control Byte
C
0
S - start condition
P - stop condition
A - Acknowledge
A - Not Acknowledge
M - I
2
C master
S' - I
2
C slave
from S' from S' from S' from S' from S'
from S' from M from M from M from M
Figure 9 I
2
C Protocol
Note1:
1. Co=“0”: The last control byte , only data bytes to follow,
Co=“1”: Next two bytes are a data byte and another control byte;
2.
CD/
=“0”: The data byte is for command operation,
CD/
=“1”: The data byte is for RAM operation.
Access to Display Data RAM and Internal Registers
This module determines whether the input data is interpreted as data or command. When A0 = “H”, the inputs at D7 - D0 are
interpreted as data and be written to display RAM. When A0 = “L”, the inputs at D7 - D0 are interpreted as command, they will
be decoded and be written to the corresponding command registers.
Display Data RAM
The Display Data RAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 X 128 bits.
For mechanical flexibility, re-mapping on segment and the direction of common outputs can be selected by software.
The Page Address Circuit
As shown in Figure 10, page address of the display data RAM is specified through the Page Address Set Command. The page
address must be specified again when changing pages to perform access in page addressing mode and it is incremented (+1)
with each display data read/write command in vertical addressing mode.