Datasheet

SH1107
15
S
1289
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
DATA OUTPUT BY
TRANSMITTER
DATA OUTPUT BY
RECEIVER
SCL FROM
MASTER
Figure 8 Acknowledge
Protocol
The SH1107 supports both read and write access. The
W/R
bit is part of the slave address. Before any data is transmitted on
the I
2
C-bus, the device that should respond is addressed first. Two 7-bit slave addresses (0111100 and 0111101) are reserved
for the SH1107. The least significant bit of the slave address is set by connecting the input SA0 to either logic 0(VSS) or 1
(VDD). The I
2
C-bus protocol is illustrated in Fig.7. The sequence is initiated with a START condition (S) from the I
2
C-bus master
that is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will
ignore the I
2
C-bus transfer. After acknowledgement, one or more command words follow which define the status of the
addressed slaves. A command word consists of a control byte, which defines Co and
C/D
(note1), plus a data byte (see Fig.9).
The last control byte is tagged with a cleared most significant bit, the continuation bit Co. After a control byte with a cleared
Co-bit, only data bytes will follow. The state of the
C/D
-bit defines whether the data-byte is interpreted as a command or as
RAM-data. The control and data bytes are also acknowledged by all addressed slaves on the bus. After the last control byte,
depending on the
C/D
bit setting, either a series of display data bytes or command data bytes may follow. If the
C/D
bit was
set to ‘1’, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended SH1107 device. If the
C/D
bit of the last control byte was set to
‘0’, these command bytes will be decoded and the setting of the device will be changed according to the received commands.
The acknowledgement after each byte is made only by the addressed slave. At the end of the transmission the I
2
C-bus master
issues a stop condition (P). If the
W/R
bit is set to one in the slave-address, the chip will output data immediately after the
slave-address according to the
C/D
bit, which was sent during the last write access. If no acknowledge is generated by the
master after a byte, the driver stops transferring data to the master.