Datasheet

SH1107
11
4 Wire Serial Interface (4-wire SPI)
The serial interface consists of serial clock SCL, serial data SI, A0 and
CS
. SI is shifted into an 8-bit shift register on every rising
edge of SCL in the order of D7, D6 and D0. A0 is sampled on every eighth clock and the data byte in the shift register is
written to the display data RAM (A0=1) or command register (A0=0) in the same clock. See Figure 3.
Table 5
IM0
IM1
IM2
Type
CS
A0
RD
WR
D0 D1 D2 to D7
0 0 0 4-wire SPI
CS
A0 - - SCL SI (Hz)
Note: - pin must always be HIGH or LOW. D7~D2 is recommended to connect the VDD or VSS. Its also allowed to leave
D7~D2 unconnected.
The serial interface is initialized when
CS
is high. In this state, SCL clock pulse or SDI data have no effect. A falling edge on
CS
enables the serial interface and indicates the start of data transmission. The SPI is also able to work properly when the
CS
always keep low, but it is not recommended.
SI (D1)
CS
1 2 3 4 5 6 7 8 9 10 11
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
A0
SCL(D0)
Figure 3 4-wire SPI data transfer
l When the chip is not active, the shift registers and the counter are reset to their initial statuses.
l Read is not possible while in serial interface mode.
l Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend the
operation be rechecked on the actual equipment.