Datasheet

SH1107
10
Data Read
address n
Dummy read
DATA
BUS holder
MPU
Internal
timing
IncrementedPreset
Set address n
Data Read
address n+1
Address preset
Read signal
Column address
(page address)
R/W
E
A0
N n n+1 n+2
N N+1 N+2
n+1N N n
Figure 2
8080-series Parallel Interface
The parallel interface consists of 8 bi-directional data pads (D7-D0),
WR
(
W/R
),
RD
(E), A0 and
CS
. The
RD
(E) input
serves as data read latch signal (clock) when it is “L” provided that
CS
= “L”. Display data or status register read is controlled by
A0 signal. The
WR
(
W/R
) input serves as data write latch signal (clock) when it is “L” and provided that
CS
= “L”. Display data
or command register write is controlled by A0 as shown in Table 3.
Table 3
IM0 IM1 IM2 Type
CS
A0
RD
WR
D0 to D7
0 1 1 8080 microprocessor bus
CS
A0
RD WR
D0 to D7
Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
Data Bus Signals
The SH1107 identifies the data bus signal according to A0,
RD
(E) and
WR
(
W/R
) signals.
Table 4
Common 6800 processor 8080 processor
A0
(
W
/
R
)
RD
WR
Function
1 1 0 1 Reads display data.
1 0 1 0 Writes display data.
0 1 0 1 Reads status.
0 0 1 0 Writes control data in internal register. (Command)