SH1107 128 X 128 Dot Matrix OLED/PLED Segment/Common Driver with Controller Features n Support maximum 128 X 128 dot matrix panel n Row re-mapping and column re-mapping n Embedded 128 X 128 bits SRAM n Vertical scrolling n Operating voltage: n On-chip oscillator - Logic voltage supply: VDD = 1.65V - 3.5V n Available internal DC-DC converter - DC-DC voltage supply: AVDD = 2.4V -3.5V n 256-step contrast control on monochrome passive OLED panel - OLED Operating voltage supply: Vpp=7.0V - 16.
SH1107 Block Diagram SEG0 SEG2...SEG126 COM0 ...COM127 SEG127...
SH1107 Pad Description Power Supply Pad NO. Symbol I/O Description 34，35 VDD 39 VDD 16，17 AVDD 25 VSS Supply Ground for analog. 26 VSS Supply Ground for logic. VSS Supply Ground for buffer. 2-6,27 68-72 Supply 1.65 - 3.5V Power supply for logic and input. O VDD output for pad option. Supply 2.4 - 3.5V power supply for the internal buffer of the DC-DC voltage converter. 37，41 VSS O Ground output for pad option.
SH1107 System Bus Connection Pads Pad NO. Symbol I/O 48 CL I/O Description This pad is the system clock input. When internal clock is enabled, this pad should be Left open. The internal clock is output from this pad. When internal oscillator is disabled, this pad receives display clock signal from external clock source. This is the internal clock enable pad. 33 CLS I CLS = “H”: Internal oscillator circuit is enabled. CLS = “L”: Internal oscillator circuit is disabled (require external input).
SH1107 OLED Drive Pads Pad NO. 271-334 Symbol I/O SEG126,124,……4,2,0 O These pads are even Segment signal output for OLED display. SEG1,3,……125,127 O These pads are odd Segment signal output for OLED display. COM127- 0 O These pads are Common signal output for OLED display. 75-138 140-220 223-269 Description Test Pads Pad NO. Symbol I/O 44 TEST1 I Test pad, internal pull low, no connection for user. 45 TEST2 O Test pad, no connection for user.
SH1107 Pad Configuration Chip Outline Dimensions Item Pad No.
SH1107 Pad Location (Total: pads) unit: Pad No.
SH1107 Pad No.
SH1107 Functional Description Microprocessor Interface Selection 2 The 8080-Parallel Interface, 6800-Parallel Interface, Serial Interface (SPI) or I C Interface can be selected by different selections of IM0~2 as shown in Table 1.
SH1107 A0 E MPU R/W DATA N N n n+1 Address preset Internal timing Read signal Preset Column address ( page address) Incremented N BUS holder N+1 N Set address n N+2 n Dummy read n+1 n+2 Data Read address n Data Read address n+1 Figure 2 8080-series Parallel Interface The parallel interface consists of 8 bi-directional data pads (D7-D0), WR ( R / W ), RD (E), A0 and CS . The RD (E) input serves as data read latch signal (clock) when it is “L” provided that CS = “L”.
SH1107 4 Wire Serial Interface (4-wire SPI) The serial interface consists of serial clock SCL, serial data SI, A0 and CS . SI is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6 … and D0. A0 is sampled on every eighth clock and the data byte in the shift register is written to the display data RAM (A0=1) or command register (A0=0) in the same clock. See Figure 3.
SH1107 3 Wire Serial Interface (3-wire SPI) The 3 wire serial interface consists of serial clock SCL, serial data SI, and CS . SI is shifted into a 9-bit shift register on every rising edge of SCL in the order of D / C , D7, D6 … D0. The D / C bit (first of the 9 bit) will determine the transferred data is written to the display data RAM ( D / C =1) or command register ( D / C =0). See Figure 4.
SH1107 2 I C-bus Interface 2 The SH1107 can transfer data via a standard I C-bus and has slave mode only in communication. The command or RAM data can be written into the chip and the status and RAM data can be read out of the chip. Table 7 IM1 IM0 0 1 IM2 Type CS A0 RD WR D0 D1 D2 to D7 I C Interface Pull Low SA0 - - SCL SDA (Hz) 2 0 Note: “-” pin must always be HIGH or LOW. D7~ D2 is recommended to connect the VDD or VSS. It is also allowed to leave D7~ D2 unconnected.
SH1107 Start and Stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). SDA SDA SCL SCL S P START condition STOP condition Figure 6 Start and Stop conditions System configuration l Transmitter: The device that sends the data to the bus.
SH1107 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 S START condition 8 9 clock pulse for acknowledgement Figure 8 Acknowledge Protocol The SH1107 supports both read and write access. The R / W bit is part of the slave address. Before any data is transmitted on 2 the I C-bus, the device that should respond is addressed first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the SH1107.
SH1107 WRITE S 0 1 1 from S' 1 1 0 S A 0 from S' 0 A 1 DC A control byte from S' A 0 DC data byte 2n>=0 bytes slave address from S' S 0 1 1 1 1 0 S A 0 1 A data byte A from M data byte A A P data byte n>=0 bytes MSB.................
SH1107 The Column Address Circuit As shown in Figure 10, the display data RAM column address is specified by the Column Address Set command. The specified column address or page address (it depends on the mode of RAM addressing) is incremented (+1) with each display data read/ write command. This allows the MPU display data to be accessed continuously.
7cH 7dH 7eH 7fH ...... 7cH 7dH 7eH 7fH Page address D0 D3 D2 D1 D0 D2 0 0 0 Segment output(ADC=0) Seg0 Seg1 Seg2 Seg3 Seg4 Seg5 Seg6 Seg7 Seg8 Seg9 Seg10 Seg11 Seg12 Seg13 Seg14 Seg15 D1 page0 D3 0 03H 02H 01H 00H D=1 7fH 7eH 7dH 7cH 7bH 7aH 79H 78H 77H 76H 75H 74H 73H 72H 71H 70H D=0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0aH 0bH 0cH 0dH 0eH 0fH ...... Common output ......
7cH 7dH 7eH 7fH ...... 7cH 7dH 7eH 7fH Page address D7 D3 D2 D1 D0 D5 D6 page15 D4 1 1 1 1 03H 02H 01H 00H D=1 7fH 7eH 7dH 7cH 7bH 7aH 79H 78H 77H 76H 75H 74H 73H 72H 71H 70H D=0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0aH 0bH 0cH 0dH 0eH 0fH ...... Common output ......
SH1107 The Oscillator Circuit This is a RC type oscillator (Figure 11) that produces the display clock. The oscillator circuit is only enabled when CLS = “H”. When CLS = “L”, the oscillation stops and the display clock is inputted through the CL terminal.
SH1107 DC-DC Voltage Converter It is a switching voltage generator circuit, designed for hand held applications. In SH1107, built-in DC-DC voltage converter accompanied with an external application circuit (shown in Figure 12) can generate a high voltage supply VPP from a low voltage supply input AVDD. VPP is the voltage supply to the OLED driver block L AVDD D (2.4~3.5) Vpp C1 VSS AVDD (2.4~3.
SH1107 Reset Circuit When the RES input falls to “L”, these reenter their default state. The default settings are shown below: 1. Display is OFF. Common and segment are in high impedance state. 2. 128 X 128 Display mode. 3. Normal segment and display data mapping (SEG0 is mapped to the top line of the display). 4. Shift register data clear in serial interface. 5. Column address counter is set at 0. 6. Contrast control register is set at 80H. 7. Normal common scan direction 8. Internal DC-DC is selected.
SH1107 Commands The SH1107 uses a combination of A0, RD (E) and WR ( R / W ) signals to identify data bus signals. As the chip analyzes and executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its busy check is usually not required. The 8080 series microprocessor interface enters a read status when a low pulse is input to the RD pad and a write status when a low pulse is input to the WR pad.
SH1107 3. Set Memory addressing mode (20H - 21H) There are two different memory addressing modes in SH1107: page addressing mode and vertical addressing mode. This command sets the way of memory addressing into one of the above two modes, “COL” means column. A0 RD (E) WR ( R / W ) D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 0 0 0 D n Page addressing mode (20H) (POR) In page addressing mode, after the display RAM is read/ written, the column address is increased automatically by 1.
SH1107 COL0 COL1 COL2 . . . COL126 COL127 PAGE15 PAGE14 .. PAGE13 PAGE1 PAGE0 Figure13-2(a) ... ... Col0 Col1 D7 D6 D6 .. .. .. ..
SH1107 n Vertical addressing mode: (21H) In vertical addressing mode, after the display RAM is read/ written, the page address is increased automatically by 1. If the page address reaches the page end address, the page address is reset to page start address and column address is not changed. Users have to set the new page and column addresses in order to access the next column. When the Segment is remapped, the direction of both page and byte are reversed.
SH1107 COL0 COL1 COL2 . . . COL126 . . . COL127 PAGE15 PAGE14 .. PAGE13 PAGE1 PAGE0 Figure13-4 (a) Col1 ... ... Col126 Col127 D7 D6 .. .. PAGE4 Col0 D1 D0 D6 .. ..
SH1107 4. Set Contrast Control Register: (Double Bytes Command) This command is to set contrast setting of the display. The chip has 256 contrast steps from 00 to FF. The segment output current increases as the contrast step value increases. Segment output current setting: ISEG = α/256 X IREF X scale factor Where: α is contrast step; IREF is reference current equals 15.
SH1107 5. Set Segment Re-map: (A0H - A1H) Change the relationship between RAM page address and segment driver. The order of segment driver output pads can be reversed by software. This allows flexible IC layout during OLED module assembly. For details, refer to the page address section of Figure 10. When display data is written or read, the column address or page address (depends on the memory addressing mode) is incremented by 1 as shown in Figure 2.
SH1107 6. Set Multiplex Ration: (Double Bytes Command) This command switches default 128 multiplex modes to any multiplex ratio from 1 to 128. The output pads COM0-COM127 will be switched to corresponding common signal.
SH1107 8. Set Normal/Reverse Display: (A6H -A7H) Reverse the display ON/OFF status without rewriting the contents of the display data RAM. A0 RD (E) WR ( R / W ) D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 1 D When D = “L”, the RAM data is high, being OLED ON potential (normal display).
SH1107 9. Set Display Offset: (Double Bytes Command) This is a double byte command. The next command specifies the mapping of display start line to one of COM0-127. For example, if COM0 is the display start line, the value is 00H; while if COM16 is the display start line, then the value should be 10H.
SH1107 11. Display OFF/ON: (AEH - AFH) Alternatively turns the display on and off. A0 RD (E) WR ( R / W ) D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 1 D When D = “L”, Display OFF OLED. (POR) When D = “H”, Display ON OLED. When the display OFF command is executed, power saver mode will be entered. Sleep mode: This mode stops every operation of the OLED display system, and can reduce current consumption nearly to a static current value if no access is made from the microprocessor.
SH1107 13. Set Common Output Scan Direction: (C0H - C8H) This command sets the scan direction of the common output allowing layout flexibility in OLED module design. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will be vertically flipped. A0 RD (E) WR ( R / W ) D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 0 D * * * When D = “L”, Scan from COM0 to COM [N -1].
SH1107 14. Set Display Clock Divide Ratio/Oscillator Frequency: (Double Bytes Command) This command is used to set the frequency of the internal display clocks (DCLKs). It is defined as the divide ratio (Value from 1 to 16) used to divide the oscillator frequency. POR is 1. Frame frequency is determined by divide ratio, number of display clocks per row and oscillator frequency.
SH1107 15. Set Dis-charge/Pre-charge Period: (Double Bytes Command) This command is used to set the duration of the pre-charge period. The interval is counted in number of DCLK. POR is 2 DCLKs.
SH1107 16. Set VCOM Deselect Level: (Double Bytes Command) This command is to set the common pad output voltage level at deselect stage. n VCOM Deselect Level Mode Set: (DBH) A0 RD (E) WR ( R / W ) D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 1 1 0 1 1 n VCOM Deselect Level Data Set: (00H - FFH) A0 RD (E) WR ( R / W ) D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 VCOMH = β1 X VREF = (0.430 + A [7:0] X 0.
SH1107 17. Set Display Start Line:（Double Bytes Command） Specify Column address to determine the initial display line or COM0. The RAM display data becomes the top line of OLED screen. It is followed by the higher number of lines in ascending order, corresponding to the duty cycle. When this command changes the Column address, the smooth scrolling or page change takes place.
SH1107 18. Read-Modify-Write: (E0H) A pair of Read-Modify-Write and End commands must always be used. In page addressing mode, once read-modify-write is issued, column address is not incremental by read display data command but incremental by write display data command only. In vertical addressing mode, once read-modify-write is issued, page address is not incremental by read display data command but incremental by write display data command only. It continues until End command is issued.
SH1107 19. End: (EEH) Cancel Read-Modify-Write mode and return column address or page address (it depends on the RAM addressing mode) to the original address (when Read-Modify-Write is issued.) A0 RD (E) WR ( R / W ) D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 Return Column address ( Page address) N N+1 N+2 N+3 N+m Read-Modify-Write mode is selected N End Figure 17 20. NOP: (E3H) No Operation Command.
SH1107 Command Table Code Command Function A0 RD WR D7 D6 D5 D4 1. Set Column Address 4 lower bits 0 1 0 0 0 0 0 2.Set Column Address 4 higher bits 0 1 0 0 0 0 1 3.Set memory addressing mode D3 D2 D1 D0 Sets 4 lower bits of column Lower column address address of display RAM in register. (POR = 00H) 0 Higher column address Sets 4 higher bits of column address of display RAM in register.
SH1107 Command Table (Continued) Code Command 11. Display OFF/ON Function A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 1 D Turns on OLED panel (1) or turns off (0). (POR = AEH) Specifies page address to load display RAM data to page address register. (POR = B0H) 12. Set Page Address 0 1 0 1 0 1 1 13 Set Common Output Scan Direction 0 1 0 1 1 0 0 D * * * Scan from COM0 to COM [N - 1] (0) or Scan from COM [N -1] to COM0 (1).
SH1107 1. Power On/Off and Initialization 1.1.
SH1107 1.2.
SH1107 1.3 Power Off Power off sequence： Note：There will be no damages to the display module if the power sequences are not met.
SH1107 Absolute Maximum Rating* *Comments DC Supply Voltage (VDD) . . . . . . . . . . .... . -0.3V to +3.6V Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended.
SH1107 DC Characteristics (Continued) Symbol Parameter Min. Typ. Max. Unit Condition VIHC High-level input voltage 0.8 X VDD - VDD V A0, D0 - D7, RD (E), WR ( R / W ), CS , VILC Low-level input voltage VSS - 0.2 X VDD V CLS, CL, IM0~2 and RES . VOHC High-level output voltage 0.8 X VDD - VDD V IOH = -0.5mA (D0 - D7, and CL). VOLC Low -level output voltage VSS - V VOLCS SDA low -level output voltage VSS - 0.2 X VDD 0.2 X VDD IOL = 0.
SH1107 AC Characteristics (1) System buses Read/Write characteristics 1 (For the 8080 Series Interface MPU) A0 tAS8 tAH8 tF CS tR tCYC8 WR , RD tCCLW tCCLR tCCHW tCCHR tDH8 tDS8 D0~D7 (WRITE) tACC8 tCH8 D0~D7 (READ) (VDD = 1.65V – 2.4V, TA = +25°C) Symbol Parameter Min. Typ. Max.
SH1107 (VDD = 2.4V – 3.5V, TA = +25°C) Symb ol Parameter Min. Typ. Max.
SH1107 (2) System buses Read/Write Characteristics 2 (For the 6800 Series Interface MPU) A0 R/W tAS6 tAH6 CS tF tR tCYC6 tEWHW tEWHR E tEWLW tDS6 tEWLR tDH6 D0~D7 (WRITE) tACC6 tOH6 D0~D7 (READ) (VDD = 1.65 – 2.4V, TA = +25°C) Parameter Symbol Min. Typ. Max.
SH1107 (VDD = 2.4 – 3.5V, TA = +25°C) Parameter Symbol Min. Typ. Max.
SH1107 (3) System buses Write characteristics 3 (For 4 wire SPI) tCSS CS tCSH tSAS tSAH A0 tSCYC tSLW SCL tSHW tF tR tSDS tF tSDH SI (VDD1 = 1.65 – 2.4V, TA = +25°C) Symbol tSCYC tSAS tSAH tSDS tSDH tCSS Parameter Serial clock cycle Address setup time Address hold time Data setup time Data hold time CS setup time Min. 500 300 300 200 200 240 Typ. - Max.
SH1107 (4) System buses Write characteristics 4(For 3 wire SPI) tCSS CS tCSH tSCYC tSLW SCL tSHW tF tR tSDS tF tSDH SI (VDD1 = 1.65 – 2.4V, TA = +25°C) Symbol tSCYC tSDS tSDH tCSS Parameter Serial clock cycle Data setup time Data hold time tCSH tSHW tSLW tR tF CS setup time Min. 500 200 200 240 Typ. - Max. - Unit ns ns ns ns CS hold time time Serial clock H pulse width Serial clock L pulse width Rise time Fall time 120 200 200 - - 30 30 ns ns ns ns ns Condition (VDD1 = 2.4 - 3.
SH1107 2 (5) I C interface characteristics SDA tBUF tF tLOW SCL tHD:START tR tHD:DATA tHIGH tSU:DATA SDA tSU:STOP tSU:START (VDD = 1.65 - 3.5V, TA = +25°C) Symbol Parameter Min. Typ. Max. Unit fSCL SCL clock frequency DC - 400 kHz TLOW SCL clock Low pulse width 1.3 - - µs THIGH SCL clock H pulse width 0.6 - - µs TSU:DATA data setup time 100 - - ns THD:DATA data hold time 0 - 0.9 µs TR SCL，SDA rise time 20+0.1Cb - 300 ns TF SCL，SDA fall time 20+0.
SH1107 (6) Reset Timing tRW RES tR Internal circuit status During reset End of reset (VDD = 1.65 - 3.5V, TA = +25°C) Symbol tR tRW Parameter Reset time Reset low pulse width Min. Typ. Max. Unit - - 2.0 µs 10.
SH1107 Application Circuit (for reference only) Reference Connection to MPU: 1. 8080 series interface: (Internal oscillator, External Vpp) C1 VDD + VDD VCL VSS VSL AVDD SW FB SENSE VBREF IM0 IM1 IM2 CS CS RES RES A0 WR A0 WR RD RD D7 - D0 D7 - D0 CL CLS + C2 External Vpp + VCOMH VPP C3 IREF R1 Figure 18-1 Note: C1 – C3: 4.7µF.
SH1107 2. 6800 Series Interface: (Internal oscillator, Built-in DC-DC) C5 AVDD C1 + VDD + AVDD VCL + C2 VSS VSL L D C3 VDD Q SW + R1 C4 + R2 R3 FB SENSE VBREF IM0 R5 C7 IM1 IM2 CS CS RES RES A0 A0 WR WR RD RD D7 - D0 SH1107 D7 - D0 CL CLS + C6 VCOMH VPP IREF R4 Figure 18-2 Note: L, D, Q, R1, R2, R3, R5 and C1---C4, C7: Please refer to following description of DC-DC module. C6:4.
SH1107 3. Serial Interface (3-wire or 4-wire SPI): (External oscillator, External VPP, Max 16.5V) VDD C1 + VDD VCL VSS VSL AVDD SW FB SENSE VBREF 3-wire SPI:IM0 Fix to VDD 4-wire SPI:IM0 Fix to VSS IM0 IM1 IM2 CS CS RES RES A0 A0 WR SH1107 Not used in 3-wire SPI,fix to VSS RD D7 - D2 D1 D0 SI SCL CL CLS External Clock C2 + External Vpp + VCOMH VPP C3 IREF R1 Figure 18-3 Note: C1---C3: 4.
SH1107 2 4. I C Interface (Internal oscillator, External VPP, Max 16.5V) VDD C1 + VDD VCL VSS VSL AVDD SW FB SENSE VBREF SH1107 IM0 IM1 IM2 Fix to VSS or VDD CS RES RES Rp Rp WR RD D7 - D2 D1 D0 SDA SCL No used,keep floating or fix all to VSS or VDD SA0 CL CLS C2 + External Vpp + VCOMH VPP C3 IREF R1 Figure 18-4 Note: C1---C3:4.
SH1107 DC-DC Below application circuit is an example for the input voltage of 3V AVDD to generate Vpp of about 15V@10mA-25mA application L AVDD D (2.4~3.5) Vpp C1 VSS AVDD (2.4~3.5) R1 SW C3 Q C2 VBREF DC-DC SENSE R3 R4 C5 FB VSS R2 C4 VSS VSS Figure 19 Symbol L D Q Value 10μH SCHOTTKY DIODE MOSFET R1 R2 R3 R4 C1 C2 C3 C4 C5 1.1M 100K 0.12 10K 22μF 0.1μF 10μF 56pF 220pF Note: R4&C5 are optional; they can increase the efficiency of inductance 60 Recommendation 20V@0.
SH1107 Ordering Information Part No.
SH1107 Data Sheet History Version 2.1 2.0 1.0 Contents P1: Added “multiplexing ratio and Vertical scrolling” description. P30: Added command “Multiplex Raiton”. P31: Added command “Display Offset”. P38: Added command “Set Display Start Line”. P42: Modify command list. P31: modify the max. value of SF P46: modify the the value of IOL when VDD1<2V Original Date Dec.2014 Dec. 2013 Jun.
