Datasheet

Table Of Contents
35.8.9 Synchronization Busy
Name:  SYNCBUSY
Offset:  0x1C
Reset:  0x00000000
Property:  -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
LENGTH CTRLB ENABLE SWRST
Access
R R R R
Reset 0 0 0 0
Bit 4 – LENGTH LENGTH Synchronization Busy
Writing to the LENGTH register requires synchronization. When writing to LENGTH,
SYNCBUSY.LENGTH will be set until synchronization is complete. If the LENGTH register is written to
while SYNCBUSY.LENGTH is asserted, an APB error is generated.
Note:  In slave mode, the clock is only running during data transfer, so SYNCBUSY.LENGTH will remain
asserted until the next data transfer begins.
Value Description
0
LENGTH synchronization is not busy.
1
LENGTH synchronization is busy.
Bit 2 – CTRLB CTRLB Synchronization Busy
Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization
is indicated by SYNCBUSY.CTRLB=1 until synchronization is complete. If CTRLB is written while
SYNCBUSY.CTRLB=1, an APB error will be generated.
Value Description
0
CTRLB synchronization is not busy.
1
CTRLB synchronization is busy.
Bit 1 – ENABLE SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing
synchronization is indicated by SYNCBUSY.ENABLE=1 until synchronization is complete.
SAM D5x/E5x Family Data Sheet
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 999