Datasheet

Table Of Contents
Mode CPOL CPHA Leading Edge Trailing Edge
0x0 0 0 Rising, sample Falling, change
0x1 0 1 Rising, change Falling, sample
0x2 1 0 Falling, sample Rising, change
0x3 1 1 Falling, change Rising, sample
Value Description
0
The data is sampled on a leading SCK edge and changed on a trailing SCK edge.
1
The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
Bits 27:24 – FORM[3:0] Frame Format
This bit field selects the various frame formats supported by the SPI in Slave mode. When the 'SPI frame
with address' format is selected, the first byte received is checked against the ADDR register.
FORM[3:0] Name Description
0x0 SPI SPI frame
0x1 - Reserved
0x2 SPI_ADDR SPI frame with address
0x3-0xF - Reserved
Bits 21:20 – DIPO[1:0] Data In Pinout
These bits define the Data In (DI) pad configurations.
In master operation, DI is MISO.
In slave operation, DI is MOSI.
These bits are not synchronized.
DIPO[1:0] Name Description
0x0 PAD[0] SERCOM PAD[0] is used as data input
0x1 PAD[1] SERCOM PAD[1] is used as data input
0x2 PAD[2] SERCOM PAD[2] is used as data input
0x3 PAD[3] SERCOM PAD[3] is used as data input
Bits 17:16 – DOPO[1:0] Data Out Pinout
This bit defines the available pad configurations for Data Out (DO) and the Serial Clock (SCK). In slave
operation, the Slave Select (SS) line is controlled by DOPO, while in master operation the SS line is
controlled by the port configuration.
In master operation, DO is MOSI.
In slave operation, DO is MISO.
These bits are not synchronized.
DOPO DO SCK Slave SS Master SS
0x0 PAD[0] PAD[1] PAD[2] PAD[2] Master SS pin when MSSEN = 1 otherwise System
configuration
SAM D5x/E5x Family Data Sheet
SERCOM SPI – SERCOM Serial Peripheral Interface
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 986