Datasheet

Table Of Contents

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Offset Name Bit Pos.

0x2C

...

0x2F

Reserved

0x30 DBGCTRL 7:0 DBGSTOP

35.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,

the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be

accessed directly.

Some registers require synchronization when read and/or written. Synchronization is denoted by the

"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.

Refer to 35.6.6 Synchronization

Some registers are enable-protected, meaning they can only be written when the module is disabled.

Enable protection is denoted by the "Enable-Protected" property in each individual register description.

Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write

Protection" property in each individual register description.

Refer to 35.5.8 Register Access Protection.

SAM D5x/E5x Family Data Sheet

SERCOM SPI – SERCOM Serial Peripheral Interface

Datasheet

DS60001507E-page 984