Datasheet

Table Of Contents

35.6.5 Sleep Mode Operation

The behavior in Sleep mode is depending on the master/slave configuration and the Run In Standby bit in

the Control A register (CTRLA.RUNSTDBY):

• Master operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will

continue to run in Idle Sleep mode and in Standby Sleep mode. Any interrupt can wake-up the

device.

• Master operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the ongoing

transaction is finished. Any interrupt can wake up the device.

• Slave operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake-up the device.

• Slave operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing

transaction.

35.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

The following bits are synchronized when written:

• Software Reset bit in the CTRLA register (CTRLA.SWRST)

• Enable bit in the CTRLA register (CTRLA.ENABLE)

• Receiver Enable bit in the CTRLB register (CTRLB.RXEN)

Note: CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB register for details.

Required write synchronization is denoted by the "Write-Synchronized" property in the register

description.

SAM D5x/E5x Family Data Sheet

SERCOM SPI – SERCOM Serial Peripheral Interface

Datasheet

DS60001507E-page 982